1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __ASM_ARM_KVM_VGIC_H 20 #define __ASM_ARM_KVM_VGIC_H 21 22 #ifdef CONFIG_KVM_NEW_VGIC 23 #include <kvm/vgic/vgic.h> 24 #else 25 26 #include <linux/kernel.h> 27 #include <linux/kvm.h> 28 #include <linux/irqreturn.h> 29 #include <linux/spinlock.h> 30 #include <linux/types.h> 31 #include <kvm/iodev.h> 32 #include <linux/irqchip/arm-gic-common.h> 33 34 #define VGIC_NR_IRQS_LEGACY 256 35 #define VGIC_NR_SGIS 16 36 #define VGIC_NR_PPIS 16 37 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 38 39 #define VGIC_V2_MAX_LRS (1 << 6) 40 #define VGIC_V3_MAX_LRS 16 41 #define VGIC_MAX_IRQS 1024 42 #define VGIC_V2_MAX_CPUS 8 43 #define VGIC_V3_MAX_CPUS 255 44 45 #if (VGIC_NR_IRQS_LEGACY & 31) 46 #error "VGIC_NR_IRQS must be a multiple of 32" 47 #endif 48 49 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) 50 #error "VGIC_NR_IRQS must be <= 1024" 51 #endif 52 53 /* 54 * The GIC distributor registers describing interrupts have two parts: 55 * - 32 per-CPU interrupts (SGI + PPI) 56 * - a bunch of shared interrupts (SPI) 57 */ 58 struct vgic_bitmap { 59 /* 60 * - One UL per VCPU for private interrupts (assumes UL is at 61 * least 32 bits) 62 * - As many UL as necessary for shared interrupts. 63 * 64 * The private interrupts are accessed via the "private" 65 * field, one UL per vcpu (the state for vcpu n is in 66 * private[n]). The shared interrupts are accessed via the 67 * "shared" pointer (IRQn state is at bit n-32 in the bitmap). 68 */ 69 unsigned long *private; 70 unsigned long *shared; 71 }; 72 73 struct vgic_bytemap { 74 /* 75 * - 8 u32 per VCPU for private interrupts 76 * - As many u32 as necessary for shared interrupts. 77 * 78 * The private interrupts are accessed via the "private" 79 * field, (the state for vcpu n is in private[n*8] to 80 * private[n*8 + 7]). The shared interrupts are accessed via 81 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the 82 * shared[(n-32)/4] word). 83 */ 84 u32 *private; 85 u32 *shared; 86 }; 87 88 struct kvm_vcpu; 89 90 enum vgic_type { 91 VGIC_V2, /* Good ol' GICv2 */ 92 VGIC_V3, /* New fancy GICv3 */ 93 }; 94 95 #define LR_STATE_PENDING (1 << 0) 96 #define LR_STATE_ACTIVE (1 << 1) 97 #define LR_STATE_MASK (3 << 0) 98 #define LR_EOI_INT (1 << 2) 99 #define LR_HW (1 << 3) 100 101 struct vgic_lr { 102 unsigned irq:10; 103 union { 104 unsigned hwirq:10; 105 unsigned source:3; 106 }; 107 unsigned state:4; 108 }; 109 110 struct vgic_vmcr { 111 u32 ctlr; 112 u32 abpr; 113 u32 bpr; 114 u32 pmr; 115 }; 116 117 struct vgic_ops { 118 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); 119 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); 120 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); 121 u64 (*get_eisr)(const struct kvm_vcpu *vcpu); 122 void (*clear_eisr)(struct kvm_vcpu *vcpu); 123 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); 124 void (*enable_underflow)(struct kvm_vcpu *vcpu); 125 void (*disable_underflow)(struct kvm_vcpu *vcpu); 126 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 127 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 128 void (*enable)(struct kvm_vcpu *vcpu); 129 }; 130 131 struct vgic_params { 132 /* vgic type */ 133 enum vgic_type type; 134 /* Physical address of vgic virtual cpu interface */ 135 phys_addr_t vcpu_base; 136 /* Number of list registers */ 137 u32 nr_lr; 138 /* Interrupt number */ 139 unsigned int maint_irq; 140 /* Virtual control interface base address */ 141 void __iomem *vctrl_base; 142 int max_gic_vcpus; 143 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 144 bool can_emulate_gicv2; 145 }; 146 147 struct vgic_vm_ops { 148 bool (*queue_sgi)(struct kvm_vcpu *, int irq); 149 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); 150 int (*init_model)(struct kvm *); 151 int (*map_resources)(struct kvm *, const struct vgic_params *); 152 }; 153 154 struct vgic_io_device { 155 gpa_t addr; 156 int len; 157 const struct vgic_io_range *reg_ranges; 158 struct kvm_vcpu *redist_vcpu; 159 struct kvm_io_device dev; 160 }; 161 162 struct irq_phys_map { 163 u32 virt_irq; 164 u32 phys_irq; 165 }; 166 167 struct irq_phys_map_entry { 168 struct list_head entry; 169 struct rcu_head rcu; 170 struct irq_phys_map map; 171 }; 172 173 struct vgic_dist { 174 spinlock_t lock; 175 bool in_kernel; 176 bool ready; 177 178 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 179 u32 vgic_model; 180 181 int nr_cpus; 182 int nr_irqs; 183 184 /* Virtual control interface mapping */ 185 void __iomem *vctrl_base; 186 187 /* Distributor and vcpu interface mapping in the guest */ 188 phys_addr_t vgic_dist_base; 189 /* GICv2 and GICv3 use different mapped register blocks */ 190 union { 191 phys_addr_t vgic_cpu_base; 192 phys_addr_t vgic_redist_base; 193 }; 194 195 /* Distributor enabled */ 196 u32 enabled; 197 198 /* Interrupt enabled (one bit per IRQ) */ 199 struct vgic_bitmap irq_enabled; 200 201 /* Level-triggered interrupt external input is asserted */ 202 struct vgic_bitmap irq_level; 203 204 /* 205 * Interrupt state is pending on the distributor 206 */ 207 struct vgic_bitmap irq_pending; 208 209 /* 210 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered 211 * interrupts. Essentially holds the state of the flip-flop in 212 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. 213 * Once set, it is only cleared for level-triggered interrupts on 214 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. 215 */ 216 struct vgic_bitmap irq_soft_pend; 217 218 /* Level-triggered interrupt queued on VCPU interface */ 219 struct vgic_bitmap irq_queued; 220 221 /* Interrupt was active when unqueue from VCPU interface */ 222 struct vgic_bitmap irq_active; 223 224 /* Interrupt priority. Not used yet. */ 225 struct vgic_bytemap irq_priority; 226 227 /* Level/edge triggered */ 228 struct vgic_bitmap irq_cfg; 229 230 /* 231 * Source CPU per SGI and target CPU: 232 * 233 * Each byte represent a SGI observable on a VCPU, each bit of 234 * this byte indicating if the corresponding VCPU has 235 * generated this interrupt. This is a GICv2 feature only. 236 * 237 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are 238 * the SGIs observable on VCPUn. 239 */ 240 u8 *irq_sgi_sources; 241 242 /* 243 * Target CPU for each SPI: 244 * 245 * Array of available SPI, each byte indicating the target 246 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32]. 247 */ 248 u8 *irq_spi_cpu; 249 250 /* 251 * Reverse lookup of irq_spi_cpu for faster compute pending: 252 * 253 * Array of bitmaps, one per VCPU, describing if IRQn is 254 * routed to a particular VCPU. 255 */ 256 struct vgic_bitmap *irq_spi_target; 257 258 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */ 259 u32 *irq_spi_mpidr; 260 261 /* Bitmap indicating which CPU has something pending */ 262 unsigned long *irq_pending_on_cpu; 263 264 /* Bitmap indicating which CPU has active IRQs */ 265 unsigned long *irq_active_on_cpu; 266 267 struct vgic_vm_ops vm_ops; 268 struct vgic_io_device dist_iodev; 269 struct vgic_io_device *redist_iodevs; 270 271 /* Virtual irq to hwirq mapping */ 272 spinlock_t irq_phys_map_lock; 273 struct list_head irq_phys_map_list; 274 }; 275 276 struct vgic_v2_cpu_if { 277 u32 vgic_hcr; 278 u32 vgic_vmcr; 279 u32 vgic_misr; /* Saved only */ 280 u64 vgic_eisr; /* Saved only */ 281 u64 vgic_elrsr; /* Saved only */ 282 u32 vgic_apr; 283 u32 vgic_lr[VGIC_V2_MAX_LRS]; 284 }; 285 286 struct vgic_v3_cpu_if { 287 #ifdef CONFIG_KVM_ARM_VGIC_V3 288 u32 vgic_hcr; 289 u32 vgic_vmcr; 290 u32 vgic_sre; /* Restored only, change ignored */ 291 u32 vgic_misr; /* Saved only */ 292 u32 vgic_eisr; /* Saved only */ 293 u32 vgic_elrsr; /* Saved only */ 294 u32 vgic_ap0r[4]; 295 u32 vgic_ap1r[4]; 296 u64 vgic_lr[VGIC_V3_MAX_LRS]; 297 #endif 298 }; 299 300 struct vgic_cpu { 301 /* Pending/active/both interrupts on this VCPU */ 302 DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS); 303 DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS); 304 DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS); 305 306 /* Pending/active/both shared interrupts, dynamically sized */ 307 unsigned long *pending_shared; 308 unsigned long *active_shared; 309 unsigned long *pend_act_shared; 310 311 /* CPU vif control registers for world switch */ 312 union { 313 struct vgic_v2_cpu_if vgic_v2; 314 struct vgic_v3_cpu_if vgic_v3; 315 }; 316 317 /* Protected by the distributor's irq_phys_map_lock */ 318 struct list_head irq_phys_map_list; 319 320 u64 live_lrs; 321 }; 322 323 #define LR_EMPTY 0xff 324 325 #define INT_STATUS_EOI (1 << 0) 326 #define INT_STATUS_UNDERFLOW (1 << 1) 327 328 struct kvm; 329 struct kvm_vcpu; 330 331 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 332 int kvm_vgic_hyp_init(void); 333 int kvm_vgic_map_resources(struct kvm *kvm); 334 int kvm_vgic_get_max_vcpus(void); 335 void kvm_vgic_early_init(struct kvm *kvm); 336 int kvm_vgic_create(struct kvm *kvm, u32 type); 337 void kvm_vgic_destroy(struct kvm *kvm); 338 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 339 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 340 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 341 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 342 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, 343 bool level); 344 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, 345 unsigned int virt_irq, bool level); 346 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 347 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 348 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, int virt_irq, int phys_irq); 349 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); 350 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); 351 352 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 353 #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) 354 #define vgic_ready(k) ((k)->arch.vgic.ready) 355 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 356 ((i) < (k)->arch.vgic.nr_irqs)) 357 358 int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info, 359 const struct vgic_ops **ops, 360 const struct vgic_params **params); 361 #ifdef CONFIG_KVM_ARM_VGIC_V3 362 int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, 363 const struct vgic_ops **ops, 364 const struct vgic_params **params); 365 #else 366 static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, 367 const struct vgic_ops **ops, 368 const struct vgic_params **params) 369 { 370 return -ENODEV; 371 } 372 #endif 373 374 #endif /* old VGIC include */ 375 #endif 376