1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Type definitions for the Microsoft Hypervisor. 4 */ 5 #ifndef _HV_HVHDK_MINI_H 6 #define _HV_HVHDK_MINI_H 7 8 #include "hvgdk_mini.h" 9 10 /* 11 * Doorbell connection_info flags. 12 */ 13 #define HV_DOORBELL_FLAG_TRIGGER_SIZE_MASK 0x00000007 14 #define HV_DOORBELL_FLAG_TRIGGER_SIZE_ANY 0x00000000 15 #define HV_DOORBELL_FLAG_TRIGGER_SIZE_BYTE 0x00000001 16 #define HV_DOORBELL_FLAG_TRIGGER_SIZE_WORD 0x00000002 17 #define HV_DOORBELL_FLAG_TRIGGER_SIZE_DWORD 0x00000003 18 #define HV_DOORBELL_FLAG_TRIGGER_SIZE_QWORD 0x00000004 19 #define HV_DOORBELL_FLAG_TRIGGER_ANY_VALUE 0x80000000 20 21 /* Each generic set contains 64 elements */ 22 #define HV_GENERIC_SET_SHIFT (6) 23 #define HV_GENERIC_SET_MASK (63) 24 25 enum hv_generic_set_format { 26 HV_GENERIC_SET_SPARSE_4K, 27 HV_GENERIC_SET_ALL, 28 }; 29 #define HV_GENERIC_SET_FORMAT hv_generic_set_format 30 31 enum hv_scheduler_type { 32 HV_SCHEDULER_TYPE_LP = 1, /* Classic scheduler w/o SMT */ 33 HV_SCHEDULER_TYPE_LP_SMT = 2, /* Classic scheduler w/ SMT */ 34 HV_SCHEDULER_TYPE_CORE_SMT = 3, /* Core scheduler */ 35 HV_SCHEDULER_TYPE_ROOT = 4, /* Root / integrated scheduler */ 36 HV_SCHEDULER_TYPE_MAX 37 }; 38 39 /* HV_STATS_AREA_TYPE */ 40 enum hv_stats_area_type { 41 HV_STATS_AREA_SELF = 0, 42 HV_STATS_AREA_PARENT = 1, 43 HV_STATS_AREA_INTERNAL = 2, 44 HV_STATS_AREA_COUNT 45 }; 46 47 enum hv_stats_object_type { 48 HV_STATS_OBJECT_HYPERVISOR = 0x00000001, 49 HV_STATS_OBJECT_LOGICAL_PROCESSOR = 0x00000002, 50 HV_STATS_OBJECT_PARTITION = 0x00010001, 51 HV_STATS_OBJECT_VP = 0x00010002 52 }; 53 54 union hv_stats_object_identity { 55 /* hv_stats_hypervisor */ 56 struct { 57 u8 reserved[15]; 58 u8 stats_area_type; 59 } __packed hv; 60 61 /* hv_stats_logical_processor */ 62 struct { 63 u32 lp_index; 64 u8 reserved[11]; 65 u8 stats_area_type; 66 } __packed lp; 67 68 /* hv_stats_partition */ 69 struct { 70 u64 partition_id; 71 u8 reserved[7]; 72 u8 stats_area_type; 73 } __packed partition; 74 75 /* hv_stats_vp */ 76 struct { 77 u64 partition_id; 78 u32 vp_index; 79 u16 flags; 80 u8 reserved; 81 u8 stats_area_type; 82 } __packed vp; 83 }; 84 85 enum hv_partition_property_code { 86 /* Privilege properties */ 87 HV_PARTITION_PROPERTY_PRIVILEGE_FLAGS = 0x00010000, 88 HV_PARTITION_PROPERTY_SYNTHETIC_PROC_FEATURES = 0x00010001, 89 90 /* Resource properties */ 91 HV_PARTITION_PROPERTY_GPA_PAGE_ACCESS_TRACKING = 0x00050005, 92 HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION = 0x00050017, 93 94 /* Compatibility properties */ 95 HV_PARTITION_PROPERTY_PROCESSOR_XSAVE_FEATURES = 0x00060002, 96 HV_PARTITION_PROPERTY_XSAVE_STATES = 0x00060007, 97 HV_PARTITION_PROPERTY_MAX_XSAVE_DATA_SIZE = 0x00060008, 98 HV_PARTITION_PROPERTY_PROCESSOR_CLOCK_FREQUENCY = 0x00060009, 99 100 /* Extended properties with larger property values */ 101 HV_PARTITION_PROPERTY_VMM_CAPABILITIES = 0x00090007, 102 }; 103 104 #define HV_PARTITION_VMM_CAPABILITIES_BANK_COUNT 1 105 #define HV_PARTITION_VMM_CAPABILITIES_RESERVED_BITFIELD_COUNT 59 106 107 struct hv_partition_property_vmm_capabilities { 108 u16 bank_count; 109 u16 reserved[3]; 110 union { 111 u64 as_uint64[HV_PARTITION_VMM_CAPABILITIES_BANK_COUNT]; 112 struct { 113 u64 map_gpa_preserve_adjustable: 1; 114 u64 vmm_can_provide_overlay_gpfn: 1; 115 u64 vp_affinity_property: 1; 116 #if IS_ENABLED(CONFIG_ARM64) 117 u64 vmm_can_provide_gic_overlay_locations: 1; 118 #else 119 u64 reservedbit3: 1; 120 #endif 121 u64 assignable_synthetic_proc_features: 1; 122 u64 reserved0: HV_PARTITION_VMM_CAPABILITIES_RESERVED_BITFIELD_COUNT; 123 } __packed; 124 }; 125 } __packed; 126 127 enum hv_snp_status { 128 HV_SNP_STATUS_NONE = 0, 129 HV_SNP_STATUS_AVAILABLE = 1, 130 HV_SNP_STATUS_INCOMPATIBLE = 2, 131 HV_SNP_STATUS_PSP_UNAVAILABLE = 3, 132 HV_SNP_STATUS_PSP_INIT_FAILED = 4, 133 HV_SNP_STATUS_PSP_BAD_FW_VERSION = 5, 134 HV_SNP_STATUS_BAD_CONFIGURATION = 6, 135 HV_SNP_STATUS_PSP_FW_UPDATE_IN_PROGRESS = 7, 136 HV_SNP_STATUS_PSP_RB_INIT_FAILED = 8, 137 HV_SNP_STATUS_PSP_PLATFORM_STATUS_FAILED = 9, 138 HV_SNP_STATUS_PSP_INIT_LATE_FAILED = 10, 139 }; 140 141 enum hv_system_property { 142 /* Add more values when needed */ 143 HV_SYSTEM_PROPERTY_SCHEDULER_TYPE = 15, 144 HV_DYNAMIC_PROCESSOR_FEATURE_PROPERTY = 21, 145 }; 146 147 enum hv_dynamic_processor_feature_property { 148 /* Add more values when needed */ 149 HV_X64_DYNAMIC_PROCESSOR_FEATURE_MAX_ENCRYPTED_PARTITIONS = 13, 150 HV_X64_DYNAMIC_PROCESSOR_FEATURE_SNP_STATUS = 16, 151 }; 152 153 struct hv_input_get_system_property { 154 u32 property_id; /* enum hv_system_property */ 155 union { 156 u32 as_uint32; 157 #if IS_ENABLED(CONFIG_X86) 158 /* enum hv_dynamic_processor_feature_property */ 159 u32 hv_processor_feature; 160 #endif 161 /* More fields to be filled in when needed */ 162 }; 163 } __packed; 164 165 struct hv_output_get_system_property { 166 union { 167 u32 scheduler_type; /* enum hv_scheduler_type */ 168 #if IS_ENABLED(CONFIG_X86) 169 u64 hv_processor_feature_value; 170 #endif 171 }; 172 } __packed; 173 174 struct hv_input_map_stats_page { 175 u32 type; /* enum hv_stats_object_type */ 176 u32 padding; 177 union hv_stats_object_identity identity; 178 } __packed; 179 180 struct hv_output_map_stats_page { 181 u64 map_location; 182 } __packed; 183 184 struct hv_input_unmap_stats_page { 185 u32 type; /* enum hv_stats_object_type */ 186 u32 padding; 187 union hv_stats_object_identity identity; 188 } __packed; 189 190 struct hv_proximity_domain_flags { 191 u32 proximity_preferred : 1; 192 u32 reserved : 30; 193 u32 proximity_info_valid : 1; 194 } __packed; 195 196 struct hv_proximity_domain_info { 197 u32 domain_id; 198 struct hv_proximity_domain_flags flags; 199 } __packed; 200 201 /* HvDepositMemory hypercall */ 202 struct hv_deposit_memory { /* HV_INPUT_DEPOSIT_MEMORY */ 203 u64 partition_id; 204 u64 gpa_page_list[]; 205 } __packed; 206 207 struct hv_input_withdraw_memory { 208 u64 partition_id; 209 struct hv_proximity_domain_info proximity_domain_info; 210 } __packed; 211 212 struct hv_output_withdraw_memory { 213 DECLARE_FLEX_ARRAY(u64, gpa_page_list); 214 } __packed; 215 216 /* HV Map GPA (Guest Physical Address) Flags */ 217 #define HV_MAP_GPA_PERMISSIONS_NONE 0x0 218 #define HV_MAP_GPA_READABLE 0x1 219 #define HV_MAP_GPA_WRITABLE 0x2 220 #define HV_MAP_GPA_KERNEL_EXECUTABLE 0x4 221 #define HV_MAP_GPA_USER_EXECUTABLE 0x8 222 #define HV_MAP_GPA_EXECUTABLE 0xC 223 #define HV_MAP_GPA_PERMISSIONS_MASK 0xF 224 #define HV_MAP_GPA_ADJUSTABLE 0x8000 225 #define HV_MAP_GPA_NO_ACCESS 0x10000 226 #define HV_MAP_GPA_NOT_CACHED 0x200000 227 #define HV_MAP_GPA_LARGE_PAGE 0x80000000 228 229 struct hv_input_map_gpa_pages { 230 u64 target_partition_id; 231 u64 target_gpa_base; 232 u32 map_flags; 233 u32 padding; 234 u64 source_gpa_page_list[]; 235 } __packed; 236 237 union hv_gpa_page_access_state_flags { 238 struct { 239 u64 clear_accessed : 1; 240 u64 set_accessed : 1; 241 u64 clear_dirty : 1; 242 u64 set_dirty : 1; 243 u64 reserved : 60; 244 } __packed; 245 u64 as_uint64; 246 }; 247 248 struct hv_input_get_gpa_pages_access_state { 249 u64 partition_id; 250 union hv_gpa_page_access_state_flags flags; 251 u64 hv_gpa_page_number; 252 } __packed; 253 254 union hv_gpa_page_access_state { 255 struct { 256 u8 accessed : 1; 257 u8 dirty : 1; 258 u8 reserved: 6; 259 }; 260 u8 as_uint8; 261 } __packed; 262 263 struct hv_lp_startup_status { 264 u64 hv_status; 265 u64 substatus1; 266 u64 substatus2; 267 u64 substatus3; 268 u64 substatus4; 269 u64 substatus5; 270 u64 substatus6; 271 } __packed; 272 273 struct hv_input_add_logical_processor { 274 u32 lp_index; 275 u32 apic_id; 276 struct hv_proximity_domain_info proximity_domain_info; 277 } __packed; 278 279 struct hv_output_add_logical_processor { 280 struct hv_lp_startup_status startup_status; 281 } __packed; 282 283 enum { /* HV_SUBNODE_TYPE */ 284 HV_SUBNODE_ANY = 0, 285 HV_SUBNODE_SOCKET, 286 HV_SUBNODE_CLUSTER, 287 HV_SUBNODE_L3, 288 HV_SUBNODE_COUNT, 289 HV_SUBNODE_INVALID = -1 290 }; 291 292 struct hv_create_vp { /* HV_INPUT_CREATE_VP */ 293 u64 partition_id; 294 u32 vp_index; 295 u8 padding[3]; 296 u8 subnode_type; 297 u64 subnode_id; 298 struct hv_proximity_domain_info proximity_domain_info; 299 u64 flags; 300 } __packed; 301 302 /* HV_INTERRUPT_TRIGGER_MODE */ 303 enum hv_interrupt_trigger_mode { 304 HV_INTERRUPT_TRIGGER_MODE_EDGE = 0, 305 HV_INTERRUPT_TRIGGER_MODE_LEVEL = 1, 306 }; 307 308 /* HV_DEVICE_INTERRUPT_DESCRIPTOR */ 309 struct hv_device_interrupt_descriptor { 310 u32 interrupt_type; 311 u32 trigger_mode; 312 u32 vector_count; 313 u32 reserved; 314 struct hv_device_interrupt_target target; 315 } __packed; 316 317 /* HV_INPUT_MAP_DEVICE_INTERRUPT */ 318 struct hv_input_map_device_interrupt { 319 u64 partition_id; 320 u64 device_id; 321 u32 flags; 322 u32 base_irt_idx; 323 struct hv_interrupt_entry logical_interrupt_entry; 324 struct hv_device_interrupt_descriptor interrupt_descriptor; 325 } __packed; 326 327 /* HV_OUTPUT_MAP_DEVICE_INTERRUPT */ 328 struct hv_output_map_device_interrupt { 329 struct hv_interrupt_entry interrupt_entry; 330 u64 ext_status_deprecated[5]; 331 } __packed; 332 333 /* HV_INPUT_UNMAP_DEVICE_INTERRUPT */ 334 struct hv_input_unmap_device_interrupt { 335 u64 partition_id; 336 u64 device_id; 337 struct hv_interrupt_entry interrupt_entry; 338 u32 flags; 339 } __packed; 340 341 #define HV_SOURCE_SHADOW_NONE 0x0 342 #define HV_SOURCE_SHADOW_BRIDGE_BUS_RANGE 0x1 343 344 struct hv_send_ipi_ex { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI_EX */ 345 u32 vector; 346 u32 reserved; 347 struct hv_vpset vp_set; 348 } __packed; 349 350 typedef u16 hv_pci_rid; /* HV_PCI_RID */ 351 typedef u16 hv_pci_segment; /* HV_PCI_SEGMENT */ 352 typedef u64 hv_logical_device_id; 353 union hv_pci_bdf { /* HV_PCI_BDF */ 354 u16 as_uint16; 355 356 struct { 357 u8 function : 3; 358 u8 device : 5; 359 u8 bus; 360 }; 361 } __packed; 362 363 union hv_pci_bus_range { 364 u16 as_uint16; 365 366 struct { 367 u8 subordinate_bus; 368 u8 secondary_bus; 369 }; 370 } __packed; 371 372 enum hv_device_type { /* HV_DEVICE_TYPE */ 373 HV_DEVICE_TYPE_LOGICAL = 0, 374 HV_DEVICE_TYPE_PCI = 1, 375 HV_DEVICE_TYPE_IOAPIC = 2, 376 HV_DEVICE_TYPE_ACPI = 3, 377 }; 378 379 union hv_device_id { /* HV_DEVICE_ID */ 380 u64 as_uint64; 381 382 struct { 383 u64 reserved0 : 62; 384 u64 device_type : 2; 385 }; 386 387 /* HV_DEVICE_TYPE_LOGICAL */ 388 struct { 389 u64 id : 62; 390 u64 device_type : 2; 391 } logical; 392 393 /* HV_DEVICE_TYPE_PCI */ 394 struct { 395 union { 396 hv_pci_rid rid; 397 union hv_pci_bdf bdf; 398 }; 399 400 hv_pci_segment segment; 401 union hv_pci_bus_range shadow_bus_range; 402 403 u16 phantom_function_bits : 2; 404 u16 source_shadow : 1; 405 406 u16 rsvdz0 : 11; 407 u16 device_type : 2; 408 } pci; 409 410 /* HV_DEVICE_TYPE_IOAPIC */ 411 struct { 412 u8 ioapic_id; 413 u8 rsvdz0; 414 u16 rsvdz1; 415 u16 rsvdz2; 416 417 u16 rsvdz3 : 14; 418 u16 device_type : 2; 419 } ioapic; 420 421 /* HV_DEVICE_TYPE_ACPI */ 422 struct { 423 u32 input_mapping_base; 424 u32 input_mapping_count : 30; 425 u32 device_type : 2; 426 } acpi; 427 } __packed; 428 429 #endif /* _HV_HVHDK_MINI_H */ 430