1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Type definitions for the Microsoft hypervisor. 4 */ 5 #ifndef _HV_HVGDK_MINI_H 6 #define _HV_HVGDK_MINI_H 7 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 11 struct hv_u128 { 12 u64 low_part; 13 u64 high_part; 14 } __packed; 15 16 /* NOTE: when adding below, update hv_result_to_string() */ 17 #define HV_STATUS_SUCCESS 0x0 18 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 19 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 20 #define HV_STATUS_INVALID_ALIGNMENT 0x4 21 #define HV_STATUS_INVALID_PARAMETER 0x5 22 #define HV_STATUS_ACCESS_DENIED 0x6 23 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 24 #define HV_STATUS_OPERATION_DENIED 0x8 25 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 26 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA 27 #define HV_STATUS_INSUFFICIENT_MEMORY 0xB 28 #define HV_STATUS_INVALID_PARTITION_ID 0xD 29 #define HV_STATUS_INVALID_VP_INDEX 0xE 30 #define HV_STATUS_NOT_FOUND 0x10 31 #define HV_STATUS_INVALID_PORT_ID 0x11 32 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 33 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 34 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 35 #define HV_STATUS_INVALID_VP_STATE 0x15 36 #define HV_STATUS_NO_RESOURCES 0x1D 37 #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 38 #define HV_STATUS_INVALID_LP_INDEX 0x41 39 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 40 #define HV_STATUS_OPERATION_FAILED 0x71 41 #define HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY 0x75 42 #define HV_STATUS_TIME_OUT 0x78 43 #define HV_STATUS_CALL_PENDING 0x79 44 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 45 46 /* 47 * The Hyper-V TimeRefCount register and the TSC 48 * page provide a guest VM clock with 100ns tick rate 49 */ 50 #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) 51 52 #define HV_HYP_PAGE_SHIFT 12 53 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 54 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 55 #define HV_HYP_LARGE_PAGE_SHIFT 21 56 57 #define HV_PARTITION_ID_INVALID ((u64)0) 58 #define HV_PARTITION_ID_SELF ((u64)-1) 59 60 /* Hyper-V specific model specific registers (MSRs) */ 61 62 #if defined(CONFIG_X86) 63 /* HV_X64_SYNTHETIC_MSR */ 64 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 65 #define HV_X64_MSR_HYPERCALL 0x40000001 66 #define HV_X64_MSR_VP_INDEX 0x40000002 67 #define HV_X64_MSR_RESET 0x40000003 68 #define HV_X64_MSR_VP_RUNTIME 0x40000010 69 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 70 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 71 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 72 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 73 74 /* Define the virtual APIC registers */ 75 #define HV_X64_MSR_EOI 0x40000070 76 #define HV_X64_MSR_ICR 0x40000071 77 #define HV_X64_MSR_TPR 0x40000072 78 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 79 80 /* Define synthetic interrupt controller model specific registers. */ 81 #define HV_X64_MSR_SCONTROL 0x40000080 82 #define HV_X64_MSR_SVERSION 0x40000081 83 #define HV_X64_MSR_SIEFP 0x40000082 84 #define HV_X64_MSR_SIMP 0x40000083 85 #define HV_X64_MSR_EOM 0x40000084 86 #define HV_X64_MSR_SIRBP 0x40000085 87 #define HV_X64_MSR_SINT0 0x40000090 88 #define HV_X64_MSR_SINT1 0x40000091 89 #define HV_X64_MSR_SINT2 0x40000092 90 #define HV_X64_MSR_SINT3 0x40000093 91 #define HV_X64_MSR_SINT4 0x40000094 92 #define HV_X64_MSR_SINT5 0x40000095 93 #define HV_X64_MSR_SINT6 0x40000096 94 #define HV_X64_MSR_SINT7 0x40000097 95 #define HV_X64_MSR_SINT8 0x40000098 96 #define HV_X64_MSR_SINT9 0x40000099 97 #define HV_X64_MSR_SINT10 0x4000009A 98 #define HV_X64_MSR_SINT11 0x4000009B 99 #define HV_X64_MSR_SINT12 0x4000009C 100 #define HV_X64_MSR_SINT13 0x4000009D 101 #define HV_X64_MSR_SINT14 0x4000009E 102 #define HV_X64_MSR_SINT15 0x4000009F 103 104 /* Define synthetic interrupt controller model specific registers for nested hypervisor */ 105 #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 106 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 107 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 108 #define HV_X64_MSR_NESTED_SIMP 0x40001083 109 #define HV_X64_MSR_NESTED_EOM 0x40001084 110 #define HV_X64_MSR_NESTED_SINT0 0x40001090 111 112 /* 113 * Synthetic Timer MSRs. Four timers per vcpu. 114 */ 115 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 116 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 117 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 118 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 119 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 120 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 121 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 122 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 123 124 /* Hyper-V guest idle MSR */ 125 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 126 127 /* Hyper-V guest crash notification MSR's */ 128 #define HV_X64_MSR_CRASH_P0 0x40000100 129 #define HV_X64_MSR_CRASH_P1 0x40000101 130 #define HV_X64_MSR_CRASH_P2 0x40000102 131 #define HV_X64_MSR_CRASH_P3 0x40000103 132 #define HV_X64_MSR_CRASH_P4 0x40000104 133 #define HV_X64_MSR_CRASH_CTL 0x40000105 134 135 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 136 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 137 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 138 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 139 140 #define HV_X64_MSR_CRASH_PARAMS \ 141 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 142 143 #define HV_IPI_LOW_VECTOR 0x10 144 #define HV_IPI_HIGH_VECTOR 0xff 145 146 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 147 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 148 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 149 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 150 151 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 152 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 153 154 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 155 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 156 157 /* Number of XMM registers used in hypercall input/output */ 158 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 159 160 struct hv_reenlightenment_control { 161 u64 vector : 8; 162 u64 reserved1 : 8; 163 u64 enabled : 1; 164 u64 reserved2 : 15; 165 u64 target_vp : 32; 166 } __packed; 167 168 struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ 169 u64 inprogress : 1; 170 u64 reserved : 63; 171 } __packed; 172 173 struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ 174 u64 enabled : 1; 175 u64 reserved : 63; 176 } __packed; 177 178 /* TSC emulation after migration */ 179 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 180 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 181 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 182 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 183 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 184 185 #endif /* CONFIG_X86 */ 186 187 struct hv_output_get_partition_id { 188 u64 partition_id; 189 } __packed; 190 191 /* HV_CRASH_CTL_REG_CONTENTS */ 192 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 193 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 194 195 union hv_reference_tsc_msr { 196 u64 as_uint64; 197 struct { 198 u64 enable : 1; 199 u64 reserved : 11; 200 u64 pfn : 52; 201 } __packed; 202 }; 203 204 /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */ 205 #define HV_MAX_SPARSE_VCPU_BANKS (64) 206 /* The number of vCPUs in one sparse bank */ 207 #define HV_VCPUS_PER_SPARSE_BANK (64) 208 209 /* 210 * Some of Hyper-V structs do not use hv_vpset where linux uses them. 211 * 212 * struct hv_vpset is usually used as part of hypercall input. The portion 213 * that counts as "fixed size input header" vs. "variable size input header" 214 * varies per hypercall. See comments at relevant hypercall call sites as to 215 * how the "valid_bank_mask" field should be accounted. 216 */ 217 struct hv_vpset { /* HV_VP_SET */ 218 u64 format; 219 u64 valid_bank_mask; 220 u64 bank_contents[]; 221 } __packed; 222 223 /* 224 * Version info reported by hypervisor 225 * Changed to a union for convenience 226 */ 227 union hv_hypervisor_version_info { 228 struct { 229 u32 build_number; 230 231 u32 minor_version : 16; 232 u32 major_version : 16; 233 234 u32 service_pack; 235 236 u32 service_number : 24; 237 u32 service_branch : 8; 238 }; 239 struct { 240 u32 eax; 241 u32 ebx; 242 u32 ecx; 243 u32 edx; 244 }; 245 }; 246 247 /* HV_CPUID_FUNCTION */ 248 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 249 #define HYPERV_CPUID_INTERFACE 0x40000001 250 #define HYPERV_CPUID_VERSION 0x40000002 251 #define HYPERV_CPUID_FEATURES 0x40000003 252 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 253 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 254 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 255 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 256 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 257 258 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 259 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 260 261 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 262 /* Support for the extended IOAPIC RTE format */ 263 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 264 #define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3) 265 266 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 267 #define HYPERV_CPUID_MIN 0x40000005 268 #define HYPERV_CPUID_MAX 0x4000ffff 269 270 /* 271 * HV_X64_HYPERVISOR_FEATURES (EAX), or 272 * HV_PARTITION_PRIVILEGE_MASK [31-0] 273 */ 274 #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0) 275 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 276 #define HV_MSR_SYNIC_AVAILABLE BIT(2) 277 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 278 #define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4) 279 #define HV_MSR_HYPERCALL_AVAILABLE BIT(5) 280 #define HV_MSR_VP_INDEX_AVAILABLE BIT(6) 281 #define HV_MSR_RESET_AVAILABLE BIT(7) 282 #define HV_MSR_STAT_PAGES_AVAILABLE BIT(8) 283 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 284 #define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10) 285 #define HV_ACCESS_FREQUENCY_MSRS BIT(11) 286 #define HV_ACCESS_REENLIGHTENMENT BIT(13) 287 #define HV_ACCESS_TSC_INVARIANT BIT(15) 288 289 /* 290 * HV_X64_HYPERVISOR_FEATURES (EBX), or 291 * HV_PARTITION_PRIVILEGE_MASK [63-32] 292 */ 293 #define HV_CREATE_PARTITIONS BIT(0) 294 #define HV_ACCESS_PARTITION_ID BIT(1) 295 #define HV_ACCESS_MEMORY_POOL BIT(2) 296 #define HV_ADJUST_MESSAGE_BUFFERS BIT(3) 297 #define HV_POST_MESSAGES BIT(4) 298 #define HV_SIGNAL_EVENTS BIT(5) 299 #define HV_CREATE_PORT BIT(6) 300 #define HV_CONNECT_PORT BIT(7) 301 #define HV_ACCESS_STATS BIT(8) 302 #define HV_DEBUGGING BIT(11) 303 #define HV_CPU_MANAGEMENT BIT(12) 304 #define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20) 305 #define HV_ISOLATION BIT(22) 306 307 #if defined(CONFIG_X86) 308 /* HV_X64_HYPERVISOR_FEATURES (EDX) */ 309 #define HV_X64_MWAIT_AVAILABLE BIT(0) 310 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 311 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 312 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 313 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 314 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 315 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 316 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 317 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 318 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 319 /* 320 * Support for returning hypercall output block via XMM 321 * registers is available 322 */ 323 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 324 /* stimer Direct Mode is available */ 325 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 326 327 /* 328 * Implementation recommendations. Indicates which behaviors the hypervisor 329 * recommends the OS implement for optimal performance. 330 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 331 */ 332 /* HV_X64_ENLIGHTENMENT_INFORMATION */ 333 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 334 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 335 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 336 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 337 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 338 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 339 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 340 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 341 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 342 #define HV_X64_HYPERV_NESTED BIT(12) 343 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 344 #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) 345 346 /* 347 * CPU management features identification. 348 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 349 */ 350 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 351 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 352 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 353 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 354 355 /* 356 * Virtual processor will never share a physical core with another virtual 357 * processor, except for virtual processors that are reported as sibling SMT 358 * threads. 359 */ 360 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 361 362 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 363 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 364 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 365 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 366 367 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 368 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 369 370 /* 371 * This is specific to AMD and specifies that enlightened TLB flush is 372 * supported. If guest opts in to this feature, ASID invalidations only 373 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 374 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 375 * or HvFlushGuestPhysicalAddressList). 376 */ 377 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 378 379 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 380 #define HV_PARAVISOR_PRESENT BIT(0) 381 382 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 383 #define HV_ISOLATION_TYPE GENMASK(3, 0) 384 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 385 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 386 387 /* HYPERV_CPUID_FEATURES.ECX bits. */ 388 #define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9) 389 #define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10) 390 391 enum hv_isolation_type { 392 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ 393 HV_ISOLATION_TYPE_VBS = 1, 394 HV_ISOLATION_TYPE_SNP = 2, 395 HV_ISOLATION_TYPE_TDX = 3 396 }; 397 398 union hv_x64_msr_hypercall_contents { 399 u64 as_uint64; 400 struct { 401 u64 enable : 1; 402 u64 reserved : 11; 403 u64 guest_physical_address : 52; 404 } __packed; 405 }; 406 #endif /* CONFIG_X86 */ 407 408 #if defined(CONFIG_ARM64) 409 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8) 410 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) 411 #endif /* CONFIG_ARM64 */ 412 413 #if defined(CONFIG_X86) 414 #define HV_MAXIMUM_PROCESSORS 2048 415 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 416 #define HV_MAXIMUM_PROCESSORS 320 417 #endif /* CONFIG_ARM64 */ 418 419 #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1) 420 #define HV_VP_INDEX_SELF ((u32)-2) 421 #define HV_ANY_VP ((u32)-1) 422 423 union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ 424 u64 as_uint64; 425 struct { 426 u64 enable : 1; 427 u64 reserved : 11; 428 u64 pfn : 52; 429 } __packed; 430 }; 431 432 /* Declare the various hypercall operations. */ 433 /* HV_CALL_CODE */ 434 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 435 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 436 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 437 #define HVCALL_SEND_IPI 0x000b 438 #define HVCALL_ENABLE_VP_VTL 0x000f 439 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 440 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 441 #define HVCALL_SEND_IPI_EX 0x0015 442 #define HVCALL_CREATE_PARTITION 0x0040 443 #define HVCALL_INITIALIZE_PARTITION 0x0041 444 #define HVCALL_FINALIZE_PARTITION 0x0042 445 #define HVCALL_DELETE_PARTITION 0x0043 446 #define HVCALL_GET_PARTITION_PROPERTY 0x0044 447 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 448 #define HVCALL_GET_PARTITION_ID 0x0046 449 #define HVCALL_DEPOSIT_MEMORY 0x0048 450 #define HVCALL_WITHDRAW_MEMORY 0x0049 451 #define HVCALL_MAP_GPA_PAGES 0x004b 452 #define HVCALL_UNMAP_GPA_PAGES 0x004c 453 #define HVCALL_INSTALL_INTERCEPT 0x004d 454 #define HVCALL_CREATE_VP 0x004e 455 #define HVCALL_DELETE_VP 0x004f 456 #define HVCALL_GET_VP_REGISTERS 0x0050 457 #define HVCALL_SET_VP_REGISTERS 0x0051 458 #define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052 459 #define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056 460 #define HVCALL_DELETE_PORT 0x0058 461 #define HVCALL_DISCONNECT_PORT 0x005b 462 #define HVCALL_POST_MESSAGE 0x005c 463 #define HVCALL_SIGNAL_EVENT 0x005d 464 #define HVCALL_POST_DEBUG_DATA 0x0069 465 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a 466 #define HVCALL_RESET_DEBUG_SESSION 0x006b 467 #define HVCALL_MAP_STATS_PAGE 0x006c 468 #define HVCALL_UNMAP_STATS_PAGE 0x006d 469 #define HVCALL_SET_SYSTEM_PROPERTY 0x006f 470 #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076 471 #define HVCALL_GET_SYSTEM_PROPERTY 0x007b 472 #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c 473 #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d 474 #define HVCALL_RETARGET_INTERRUPT 0x007e 475 #define HVCALL_NOTIFY_PARTITION_EVENT 0x0087 476 #define HVCALL_ENTER_SLEEP_STATE 0x0084 477 #define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b 478 #define HVCALL_SCRUB_PARTITION 0x008d 479 #define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091 480 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094 481 #define HVCALL_CREATE_PORT 0x0095 482 #define HVCALL_CONNECT_PORT 0x0096 483 #define HVCALL_START_VP 0x0099 484 #define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a 485 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 486 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 487 #define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0 488 #define HVCALL_POST_MESSAGE_DIRECT 0x00c1 489 #define HVCALL_DISPATCH_VP 0x00c2 490 #define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9 491 #define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7 492 #define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8 493 #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db 494 #define HVCALL_MAP_VP_STATE_PAGE 0x00e1 495 #define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2 496 #define HVCALL_GET_VP_STATE 0x00e3 497 #define HVCALL_SET_VP_STATE 0x00e4 498 #define HVCALL_GET_VP_CPUID_VALUES 0x00f4 499 #define HVCALL_GET_PARTITION_PROPERTY_EX 0x0101 500 #define HVCALL_MMIO_READ 0x0106 501 #define HVCALL_MMIO_WRITE 0x0107 502 #define HVCALL_DISABLE_HYP_EX 0x010f 503 #define HVCALL_MAP_STATS_PAGE2 0x0131 504 505 /* HV_HYPERCALL_INPUT */ 506 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 507 #define HV_HYPERCALL_FAST_BIT BIT(16) 508 #define HV_HYPERCALL_VARHEAD_OFFSET 17 509 #define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17) 510 #define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27) 511 #define HV_HYPERCALL_NESTED BIT_ULL(31) 512 #define HV_HYPERCALL_REP_COMP_OFFSET 32 513 #define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32) 514 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 515 #define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44) 516 #define HV_HYPERCALL_REP_START_OFFSET 48 517 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 518 #define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60) 519 #define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \ 520 HV_HYPERCALL_RSVD1_MASK | \ 521 HV_HYPERCALL_RSVD2_MASK) 522 523 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 524 struct hv_guest_mapping_flush { 525 u64 address_space; 526 u64 flags; 527 } __packed; 528 529 /* 530 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 531 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 532 */ 533 #define HV_MAX_FLUSH_PAGES (2048) 534 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0 535 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1 536 537 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 538 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 539 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 540 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 541 542 /* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */ 543 union hv_gpa_page_range { 544 u64 address_space; 545 struct { 546 u64 additional_pages : 11; 547 u64 largepage : 1; 548 u64 basepfn : 52; 549 } page; 550 struct { 551 u64 reserved : 12; 552 u64 page_size : 1; 553 u64 reserved1 : 8; 554 u64 base_large_pfn : 43; 555 }; 556 }; 557 558 /* 559 * All input flush parameters should be in single page. The max flush 560 * count is equal with how many entries of union hv_gpa_page_range can 561 * be populated into the input parameter page. 562 */ 563 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 564 sizeof(union hv_gpa_page_range)) 565 566 struct hv_guest_mapping_flush_list { 567 u64 address_space; 568 u64 flags; 569 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 570 }; 571 572 struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */ 573 u64 address_space; 574 u64 flags; 575 u64 processor_mask; 576 u64 gva_list[]; 577 } __packed; 578 579 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 580 struct hv_tlb_flush_ex { 581 u64 address_space; 582 u64 flags; 583 __TRAILING_OVERLAP(struct hv_vpset, hv_vp_set, bank_contents, __packed, 584 u64 gva_list[]; 585 ); 586 } __packed; 587 static_assert(offsetof(struct hv_tlb_flush_ex, hv_vp_set.bank_contents) == 588 offsetof(struct hv_tlb_flush_ex, gva_list)); 589 590 struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */ 591 volatile u32 tsc_sequence; 592 u32 reserved1; 593 volatile u64 tsc_scale; 594 volatile s64 tsc_offset; 595 } __packed; 596 597 /* Define the number of synthetic interrupt sources. */ 598 #define HV_SYNIC_SINT_COUNT (16) 599 600 /* Define the expected SynIC version. */ 601 #define HV_SYNIC_VERSION_1 (0x1) 602 /* Valid SynIC vectors are 16-255. */ 603 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 604 605 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 606 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 607 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 608 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 609 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 610 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 611 612 /* Hyper-V defined statically assigned SINTs */ 613 #define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000 614 #define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001 615 #define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002 616 #define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005 617 618 /* mshv assigned SINT for doorbell */ 619 #define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX 620 621 enum hv_interrupt_type { 622 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 623 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 624 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 625 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 626 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 627 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 628 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 629 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 630 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 631 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 632 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 633 }; 634 635 /* Define synthetic interrupt source. */ 636 union hv_synic_sint { 637 u64 as_uint64; 638 struct { 639 u64 vector : 8; 640 u64 reserved1 : 8; 641 u64 masked : 1; 642 u64 auto_eoi : 1; 643 u64 polling : 1; 644 u64 as_intercept : 1; 645 u64 proxy : 1; 646 u64 reserved2 : 43; 647 } __packed; 648 }; 649 650 union hv_x64_xsave_xfem_register { 651 u64 as_uint64; 652 struct { 653 u32 low_uint32; 654 u32 high_uint32; 655 } __packed; 656 struct { 657 u64 legacy_x87 : 1; 658 u64 legacy_sse : 1; 659 u64 avx : 1; 660 u64 mpx_bndreg : 1; 661 u64 mpx_bndcsr : 1; 662 u64 avx_512_op_mask : 1; 663 u64 avx_512_zmmhi : 1; 664 u64 avx_512_zmm16_31 : 1; 665 u64 rsvd8_9 : 2; 666 u64 pasid : 1; 667 u64 cet_u : 1; 668 u64 cet_s : 1; 669 u64 rsvd13_16 : 4; 670 u64 xtile_cfg : 1; 671 u64 xtile_data : 1; 672 u64 rsvd19_63 : 45; 673 } __packed; 674 }; 675 676 /* Synthetic timer configuration */ 677 union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */ 678 u64 as_uint64; 679 struct { 680 u64 enable : 1; 681 u64 periodic : 1; 682 u64 lazy : 1; 683 u64 auto_enable : 1; 684 u64 apic_vector : 8; 685 u64 direct_mode : 1; 686 u64 reserved_z0 : 3; 687 u64 sintx : 4; 688 u64 reserved_z1 : 44; 689 } __packed; 690 }; 691 692 /* Define the number of synthetic timers */ 693 #define HV_SYNIC_STIMER_COUNT (4) 694 695 /* Define port identifier type. */ 696 union hv_port_id { 697 u32 asu32; 698 struct { 699 u32 id : 24; 700 u32 reserved : 8; 701 } __packed u; 702 }; 703 704 #define HV_MESSAGE_SIZE (256) 705 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 706 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 707 708 /* Define hypervisor message types. */ 709 enum hv_message_type { 710 HVMSG_NONE = 0x00000000, 711 712 /* Memory access messages. */ 713 HVMSG_UNMAPPED_GPA = 0x80000000, 714 HVMSG_GPA_INTERCEPT = 0x80000001, 715 716 /* Timer notification messages. */ 717 HVMSG_TIMER_EXPIRED = 0x80000010, 718 719 /* Error messages. */ 720 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 721 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 722 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 723 724 /* 725 * Opaque intercept message. The original intercept message is only 726 * accessible from the mapped intercept message page. 727 */ 728 HVMSG_OPAQUE_INTERCEPT = 0x8000003F, 729 730 /* Trace buffer complete messages. */ 731 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 732 733 /* Hypercall intercept */ 734 HVMSG_HYPERCALL_INTERCEPT = 0x80000050, 735 736 /* SynIC intercepts */ 737 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060, 738 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061, 739 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062, 740 741 /* Async call completion intercept */ 742 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070, 743 744 /* Root scheduler messages */ 745 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100, 746 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101, 747 748 /* Platform-specific processor intercept messages. */ 749 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000, 750 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 751 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 752 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 753 HVMSG_X64_APIC_EOI = 0x80010004, 754 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005, 755 HVMSG_X64_IOMMU_PRQ = 0x80010006, 756 HVMSG_X64_HALT = 0x80010007, 757 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008, 758 HVMSG_X64_SIPI_INTERCEPT = 0x80010009, 759 }; 760 761 /* Define the format of the SIMP register */ 762 union hv_synic_simp { 763 u64 as_uint64; 764 struct { 765 u64 simp_enabled : 1; 766 u64 preserved : 11; 767 u64 base_simp_gpa : 52; 768 } __packed; 769 }; 770 771 union hv_message_flags { 772 u8 asu8; 773 struct { 774 u8 msg_pending : 1; 775 u8 reserved : 7; 776 } __packed; 777 }; 778 779 struct hv_message_header { 780 u32 message_type; 781 u8 payload_size; 782 union hv_message_flags message_flags; 783 u8 reserved[2]; 784 union { 785 u64 sender; 786 union hv_port_id port; 787 }; 788 } __packed; 789 790 /* 791 * Message format for notifications delivered via 792 * intercept message(as_intercept=1) 793 */ 794 struct hv_notification_message_payload { 795 u32 sint_index; 796 } __packed; 797 798 struct hv_message { 799 struct hv_message_header header; 800 union { 801 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 802 } u; 803 } __packed; 804 805 /* Define the synthetic interrupt message page layout. */ 806 struct hv_message_page { 807 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 808 } __packed; 809 810 /* Define timer message payload structure. */ 811 struct hv_timer_message_payload { 812 u32 timer_index; 813 u32 reserved; 814 u64 expiration_time; /* When the timer expired */ 815 u64 delivery_time; /* When the message was delivered */ 816 } __packed; 817 818 struct hv_x64_segment_register { 819 u64 base; 820 u32 limit; 821 u16 selector; 822 union { 823 struct { 824 u16 segment_type : 4; 825 u16 non_system_segment : 1; 826 u16 descriptor_privilege_level : 2; 827 u16 present : 1; 828 u16 reserved : 4; 829 u16 available : 1; 830 u16 _long : 1; 831 u16 _default : 1; 832 u16 granularity : 1; 833 } __packed; 834 u16 attributes; 835 }; 836 } __packed; 837 838 struct hv_x64_table_register { 839 u16 pad[3]; 840 u16 limit; 841 u64 base; 842 } __packed; 843 844 #define HV_NORMAL_VTL 0 845 846 union hv_input_vtl { 847 u8 as_uint8; 848 struct { 849 u8 target_vtl : 4; 850 u8 use_target_vtl : 1; 851 u8 reserved_z : 3; 852 }; 853 } __packed; 854 855 struct hv_init_vp_context { 856 u64 rip; 857 u64 rsp; 858 u64 rflags; 859 860 struct hv_x64_segment_register cs; 861 struct hv_x64_segment_register ds; 862 struct hv_x64_segment_register es; 863 struct hv_x64_segment_register fs; 864 struct hv_x64_segment_register gs; 865 struct hv_x64_segment_register ss; 866 struct hv_x64_segment_register tr; 867 struct hv_x64_segment_register ldtr; 868 869 struct hv_x64_table_register idtr; 870 struct hv_x64_table_register gdtr; 871 872 u64 efer; 873 u64 cr0; 874 u64 cr3; 875 u64 cr4; 876 u64 msr_cr_pat; 877 } __packed; 878 879 struct hv_enable_vp_vtl { 880 u64 partition_id; 881 u32 vp_index; 882 union hv_input_vtl target_vtl; 883 u8 mbz0; 884 u16 mbz1; 885 struct hv_init_vp_context vp_context; 886 } __packed; 887 888 struct hv_get_vp_from_apic_id_in { 889 u64 partition_id; 890 union hv_input_vtl target_vtl; 891 u8 res[7]; 892 u32 apic_ids[]; 893 } __packed; 894 895 union hv_register_vsm_partition_config { 896 u64 as_uint64; 897 struct { 898 u64 enable_vtl_protection : 1; 899 u64 default_vtl_protection_mask : 4; 900 u64 zero_memory_on_reset : 1; 901 u64 deny_lower_vtl_startup : 1; 902 u64 intercept_acceptance : 1; 903 u64 intercept_enable_vtl_protection : 1; 904 u64 intercept_vp_startup : 1; 905 u64 intercept_cpuid_unimplemented : 1; 906 u64 intercept_unrecoverable_exception : 1; 907 u64 intercept_page : 1; 908 u64 mbz : 51; 909 } __packed; 910 }; 911 912 union hv_register_vsm_capabilities { 913 u64 as_uint64; 914 struct { 915 u64 dr6_shared: 1; 916 u64 mbec_vtl_mask: 16; 917 u64 deny_lower_vtl_startup: 1; 918 u64 supervisor_shadow_stack: 1; 919 u64 hardware_hvpt_available: 1; 920 u64 software_hvpt_available: 1; 921 u64 hardware_hvpt_range_bits: 6; 922 u64 intercept_page_available: 1; 923 u64 return_action_available: 1; 924 u64 reserved: 35; 925 } __packed; 926 }; 927 928 union hv_register_vsm_page_offsets { 929 struct { 930 u64 vtl_call_offset : 12; 931 u64 vtl_return_offset : 12; 932 u64 reserved_mbz : 40; 933 } __packed; 934 u64 as_uint64; 935 }; 936 937 struct hv_nested_enlightenments_control { 938 struct { 939 u32 directhypercall : 1; 940 u32 reserved : 31; 941 } __packed features; 942 struct { 943 u32 inter_partition_comm : 1; 944 u32 reserved : 31; 945 } __packed hypercall_controls; 946 } __packed; 947 948 /* Define virtual processor assist page structure. */ 949 struct hv_vp_assist_page { 950 u32 apic_assist; 951 u32 reserved1; 952 u32 vtl_entry_reason; 953 u32 vtl_reserved; 954 u64 vtl_ret_x64rax; 955 u64 vtl_ret_x64rcx; 956 struct hv_nested_enlightenments_control nested_control; 957 u8 enlighten_vmentry; 958 u8 reserved2[7]; 959 u64 current_nested_vmcs; 960 u8 synthetic_time_unhalted_timer_expired; 961 u8 reserved3[7]; 962 u8 virtualization_fault_information[40]; 963 u8 reserved4[8]; 964 u8 intercept_message[256]; 965 u8 vtl_ret_actions[256]; 966 } __packed; 967 968 enum hv_register_name { 969 /* Suspend Registers */ 970 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000, 971 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001, 972 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003, 973 974 /* Version - 128-bit result same as CPUID 0x40000002 */ 975 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100, 976 977 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */ 978 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200, 979 HV_REGISTER_FEATURES_INFO = 0x00000201, 980 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202, 981 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203, 982 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204, 983 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205, 984 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206, 985 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207, 986 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208, 987 988 /* Guest Crash Registers */ 989 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210, 990 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211, 991 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212, 992 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213, 993 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214, 994 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215, 995 996 /* Misc */ 997 HV_REGISTER_VP_RUNTIME = 0x00090000, 998 HV_REGISTER_GUEST_OS_ID = 0x00090002, 999 HV_REGISTER_VP_INDEX = 0x00090003, 1000 HV_REGISTER_TIME_REF_COUNT = 0x00090004, 1001 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007, 1002 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013, 1003 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014, 1004 HV_REGISTER_REFERENCE_TSC = 0x00090017, 1005 1006 /* Hypervisor-defined Registers (Synic) */ 1007 HV_REGISTER_SINT0 = 0x000A0000, 1008 HV_REGISTER_SINT1 = 0x000A0001, 1009 HV_REGISTER_SINT2 = 0x000A0002, 1010 HV_REGISTER_SINT3 = 0x000A0003, 1011 HV_REGISTER_SINT4 = 0x000A0004, 1012 HV_REGISTER_SINT5 = 0x000A0005, 1013 HV_REGISTER_SINT6 = 0x000A0006, 1014 HV_REGISTER_SINT7 = 0x000A0007, 1015 HV_REGISTER_SINT8 = 0x000A0008, 1016 HV_REGISTER_SINT9 = 0x000A0009, 1017 HV_REGISTER_SINT10 = 0x000A000A, 1018 HV_REGISTER_SINT11 = 0x000A000B, 1019 HV_REGISTER_SINT12 = 0x000A000C, 1020 HV_REGISTER_SINT13 = 0x000A000D, 1021 HV_REGISTER_SINT14 = 0x000A000E, 1022 HV_REGISTER_SINT15 = 0x000A000F, 1023 HV_REGISTER_SCONTROL = 0x000A0010, 1024 HV_REGISTER_SVERSION = 0x000A0011, 1025 HV_REGISTER_SIEFP = 0x000A0012, 1026 HV_REGISTER_SIMP = 0x000A0013, 1027 HV_REGISTER_EOM = 0x000A0014, 1028 HV_REGISTER_SIRBP = 0x000A0015, 1029 1030 HV_REGISTER_NESTED_SINT0 = 0x000A1000, 1031 HV_REGISTER_NESTED_SINT1 = 0x000A1001, 1032 HV_REGISTER_NESTED_SINT2 = 0x000A1002, 1033 HV_REGISTER_NESTED_SINT3 = 0x000A1003, 1034 HV_REGISTER_NESTED_SINT4 = 0x000A1004, 1035 HV_REGISTER_NESTED_SINT5 = 0x000A1005, 1036 HV_REGISTER_NESTED_SINT6 = 0x000A1006, 1037 HV_REGISTER_NESTED_SINT7 = 0x000A1007, 1038 HV_REGISTER_NESTED_SINT8 = 0x000A1008, 1039 HV_REGISTER_NESTED_SINT9 = 0x000A1009, 1040 HV_REGISTER_NESTED_SINT10 = 0x000A100A, 1041 HV_REGISTER_NESTED_SINT11 = 0x000A100B, 1042 HV_REGISTER_NESTED_SINT12 = 0x000A100C, 1043 HV_REGISTER_NESTED_SINT13 = 0x000A100D, 1044 HV_REGISTER_NESTED_SINT14 = 0x000A100E, 1045 HV_REGISTER_NESTED_SINT15 = 0x000A100F, 1046 HV_REGISTER_NESTED_SCONTROL = 0x000A1010, 1047 HV_REGISTER_NESTED_SVERSION = 0x000A1011, 1048 HV_REGISTER_NESTED_SIFP = 0x000A1012, 1049 HV_REGISTER_NESTED_SIPP = 0x000A1013, 1050 HV_REGISTER_NESTED_EOM = 0x000A1014, 1051 HV_REGISTER_NESTED_SIRBP = 0x000a1015, 1052 1053 /* Hypervisor-defined Registers (Synthetic Timers) */ 1054 HV_REGISTER_STIMER0_CONFIG = 0x000B0000, 1055 HV_REGISTER_STIMER0_COUNT = 0x000B0001, 1056 1057 /* VSM */ 1058 HV_REGISTER_VSM_VP_STATUS = 0x000D0003, 1059 1060 /* Synthetic VSM registers */ 1061 HV_REGISTER_VSM_CODE_PAGE_OFFSETS = 0x000D0002, 1062 HV_REGISTER_VSM_CAPABILITIES = 0x000D0006, 1063 HV_REGISTER_VSM_PARTITION_CONFIG = 0x000D0007, 1064 1065 #if defined(CONFIG_X86) 1066 /* X64 Debug Registers */ 1067 HV_X64_REGISTER_DR0 = 0x00050000, 1068 HV_X64_REGISTER_DR1 = 0x00050001, 1069 HV_X64_REGISTER_DR2 = 0x00050002, 1070 HV_X64_REGISTER_DR3 = 0x00050003, 1071 HV_X64_REGISTER_DR6 = 0x00050004, 1072 HV_X64_REGISTER_DR7 = 0x00050005, 1073 1074 /* X64 Cache control MSRs */ 1075 HV_X64_REGISTER_MSR_MTRR_CAP = 0x0008000D, 1076 HV_X64_REGISTER_MSR_MTRR_DEF_TYPE = 0x0008000E, 1077 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 = 0x00080010, 1078 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1 = 0x00080011, 1079 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2 = 0x00080012, 1080 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3 = 0x00080013, 1081 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4 = 0x00080014, 1082 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5 = 0x00080015, 1083 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6 = 0x00080016, 1084 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7 = 0x00080017, 1085 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8 = 0x00080018, 1086 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9 = 0x00080019, 1087 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA = 0x0008001A, 1088 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB = 0x0008001B, 1089 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC = 0x0008001C, 1090 HV_X64_REGISTER_MSR_MTRR_PHYS_BASED = 0x0008001D, 1091 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE = 0x0008001E, 1092 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF = 0x0008001F, 1093 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 = 0x00080040, 1094 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1 = 0x00080041, 1095 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2 = 0x00080042, 1096 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3 = 0x00080043, 1097 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4 = 0x00080044, 1098 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5 = 0x00080045, 1099 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6 = 0x00080046, 1100 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7 = 0x00080047, 1101 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8 = 0x00080048, 1102 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9 = 0x00080049, 1103 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA = 0x0008004A, 1104 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB = 0x0008004B, 1105 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC = 0x0008004C, 1106 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD = 0x0008004D, 1107 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE = 0x0008004E, 1108 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF = 0x0008004F, 1109 HV_X64_REGISTER_MSR_MTRR_FIX64K00000 = 0x00080070, 1110 HV_X64_REGISTER_MSR_MTRR_FIX16K80000 = 0x00080071, 1111 HV_X64_REGISTER_MSR_MTRR_FIX16KA0000 = 0x00080072, 1112 HV_X64_REGISTER_MSR_MTRR_FIX4KC0000 = 0x00080073, 1113 HV_X64_REGISTER_MSR_MTRR_FIX4KC8000 = 0x00080074, 1114 HV_X64_REGISTER_MSR_MTRR_FIX4KD0000 = 0x00080075, 1115 HV_X64_REGISTER_MSR_MTRR_FIX4KD8000 = 0x00080076, 1116 HV_X64_REGISTER_MSR_MTRR_FIX4KE0000 = 0x00080077, 1117 HV_X64_REGISTER_MSR_MTRR_FIX4KE8000 = 0x00080078, 1118 HV_X64_REGISTER_MSR_MTRR_FIX4KF0000 = 0x00080079, 1119 HV_X64_REGISTER_MSR_MTRR_FIX4KF8000 = 0x0008007A, 1120 1121 HV_X64_REGISTER_REG_PAGE = 0x0009001C, 1122 #endif 1123 }; 1124 1125 /* 1126 * Arch compatibility regs for use with hv_set/get_register 1127 */ 1128 #if defined(CONFIG_X86) 1129 1130 /* 1131 * To support arch-generic code calling hv_set/get_register: 1132 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq 1133 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 1134 */ 1135 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0) 1136 #define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1) 1137 #define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2) 1138 #define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3) 1139 #define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4) 1140 #define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL) 1141 1142 #define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX) 1143 #define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) 1144 #define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) 1145 1146 #define HV_MSR_SINT0 (HV_X64_MSR_SINT0) 1147 #define HV_MSR_SVERSION (HV_X64_MSR_SVERSION) 1148 #define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL) 1149 #define HV_MSR_SIEFP (HV_X64_MSR_SIEFP) 1150 #define HV_MSR_SIMP (HV_X64_MSR_SIMP) 1151 #define HV_MSR_EOM (HV_X64_MSR_EOM) 1152 #define HV_MSR_SIRBP (HV_X64_MSR_SIRBP) 1153 1154 #define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL) 1155 #define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION) 1156 #define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP) 1157 #define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP) 1158 #define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM) 1159 #define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0) 1160 1161 #define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) 1162 #define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) 1163 1164 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1165 1166 #define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0) 1167 #define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1) 1168 #define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2) 1169 #define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3) 1170 #define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4) 1171 #define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL) 1172 1173 #define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX) 1174 #define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) 1175 #define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) 1176 1177 #define HV_MSR_SINT0 (HV_REGISTER_SINT0) 1178 #define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL) 1179 #define HV_MSR_SIEFP (HV_REGISTER_SIEFP) 1180 #define HV_MSR_SIMP (HV_REGISTER_SIMP) 1181 #define HV_MSR_EOM (HV_REGISTER_EOM) 1182 #define HV_MSR_SIRBP (HV_REGISTER_SIRBP) 1183 1184 #define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) 1185 #define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) 1186 1187 #endif /* CONFIG_ARM64 */ 1188 1189 union hv_explicit_suspend_register { 1190 u64 as_uint64; 1191 struct { 1192 u64 suspended : 1; 1193 u64 reserved : 63; 1194 } __packed; 1195 }; 1196 1197 union hv_intercept_suspend_register { 1198 u64 as_uint64; 1199 struct { 1200 u64 suspended : 1; 1201 u64 reserved : 63; 1202 } __packed; 1203 }; 1204 1205 union hv_dispatch_suspend_register { 1206 u64 as_uint64; 1207 struct { 1208 u64 suspended : 1; 1209 u64 reserved : 63; 1210 } __packed; 1211 }; 1212 1213 union hv_arm64_pending_interruption_register { 1214 u64 as_uint64; 1215 struct { 1216 u64 interruption_pending : 1; 1217 u64 interruption_type: 1; 1218 u64 reserved : 30; 1219 u64 error_code : 32; 1220 } __packed; 1221 }; 1222 1223 union hv_arm64_interrupt_state_register { 1224 u64 as_uint64; 1225 struct { 1226 u64 interrupt_shadow : 1; 1227 u64 reserved : 63; 1228 } __packed; 1229 }; 1230 1231 union hv_arm64_pending_synthetic_exception_event { 1232 u64 as_uint64[2]; 1233 struct { 1234 u8 event_pending : 1; 1235 u8 event_type : 3; 1236 u8 reserved : 4; 1237 u8 rsvd[3]; 1238 u32 exception_type; 1239 u64 context; 1240 } __packed; 1241 }; 1242 1243 union hv_x64_interrupt_state_register { 1244 u64 as_uint64; 1245 struct { 1246 u64 interrupt_shadow : 1; 1247 u64 nmi_masked : 1; 1248 u64 reserved : 62; 1249 } __packed; 1250 }; 1251 1252 union hv_x64_pending_interruption_register { 1253 u64 as_uint64; 1254 struct { 1255 u32 interruption_pending : 1; 1256 u32 interruption_type : 3; 1257 u32 deliver_error_code : 1; 1258 u32 instruction_length : 4; 1259 u32 nested_event : 1; 1260 u32 reserved : 6; 1261 u32 interruption_vector : 16; 1262 u32 error_code; 1263 } __packed; 1264 }; 1265 1266 union hv_register_value { 1267 struct hv_u128 reg128; 1268 u64 reg64; 1269 u32 reg32; 1270 u16 reg16; 1271 u8 reg8; 1272 1273 struct hv_x64_segment_register segment; 1274 struct hv_x64_table_register table; 1275 union hv_explicit_suspend_register explicit_suspend; 1276 union hv_intercept_suspend_register intercept_suspend; 1277 union hv_dispatch_suspend_register dispatch_suspend; 1278 #ifdef CONFIG_ARM64 1279 union hv_arm64_interrupt_state_register interrupt_state; 1280 union hv_arm64_pending_interruption_register pending_interruption; 1281 #endif 1282 #ifdef CONFIG_X86 1283 union hv_x64_interrupt_state_register interrupt_state; 1284 union hv_x64_pending_interruption_register pending_interruption; 1285 #endif 1286 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event; 1287 }; 1288 1289 /* NOTE: Linux helper struct - NOT from Hyper-V code. */ 1290 struct hv_output_get_vp_registers { 1291 DECLARE_FLEX_ARRAY(union hv_register_value, values); 1292 }; 1293 1294 #if defined(CONFIG_ARM64) 1295 /* HvGetVpRegisters returns an array of these output elements */ 1296 struct hv_get_vp_registers_output { 1297 union { 1298 struct { 1299 u32 a; 1300 u32 b; 1301 u32 c; 1302 u32 d; 1303 } as32 __packed; 1304 struct { 1305 u64 low; 1306 u64 high; 1307 } as64 __packed; 1308 }; 1309 }; 1310 1311 #endif /* CONFIG_ARM64 */ 1312 1313 struct hv_register_assoc { 1314 u32 name; /* enum hv_register_name */ 1315 u32 reserved1; 1316 u64 reserved2; 1317 union hv_register_value value; 1318 } __packed; 1319 1320 struct hv_input_get_vp_registers { 1321 u64 partition_id; 1322 u32 vp_index; 1323 union hv_input_vtl input_vtl; 1324 u8 rsvd_z8; 1325 u16 rsvd_z16; 1326 u32 names[]; 1327 } __packed; 1328 1329 struct hv_input_set_vp_registers { 1330 u64 partition_id; 1331 u32 vp_index; 1332 union hv_input_vtl input_vtl; 1333 u8 rsvd_z8; 1334 u16 rsvd_z16; 1335 struct hv_register_assoc elements[]; 1336 } __packed; 1337 1338 #define HV_UNMAP_GPA_LARGE_PAGE 0x2 1339 1340 /* HvCallSendSyntheticClusterIpi hypercall */ 1341 struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */ 1342 u32 vector; 1343 u32 reserved; 1344 u64 cpu_mask; 1345 } __packed; 1346 1347 #define HV_VTL_MASK GENMASK(3, 0) 1348 1349 /* Hyper-V memory host visibility */ 1350 enum hv_mem_host_visibility { 1351 VMBUS_PAGE_NOT_VISIBLE = 0, 1352 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 1353 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 1354 }; 1355 1356 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 1357 #define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2) 1358 struct hv_gpa_range_for_visibility { 1359 u64 partition_id; 1360 u32 host_visibility : 2; 1361 u32 reserved0 : 30; 1362 u32 reserved1; 1363 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 1364 } __packed; 1365 1366 #if defined(CONFIG_X86) 1367 union hv_msi_address_register { /* HV_MSI_ADDRESS */ 1368 u32 as_uint32; 1369 struct { 1370 u32 reserved1 : 2; 1371 u32 destination_mode : 1; 1372 u32 redirection_hint : 1; 1373 u32 reserved2 : 8; 1374 u32 destination_id : 8; 1375 u32 msi_base : 12; 1376 }; 1377 } __packed; 1378 1379 union hv_msi_data_register { /* HV_MSI_ENTRY.Data */ 1380 u32 as_uint32; 1381 struct { 1382 u32 vector : 8; 1383 u32 delivery_mode : 3; 1384 u32 reserved1 : 3; 1385 u32 level_assert : 1; 1386 u32 trigger_mode : 1; 1387 u32 reserved2 : 16; 1388 }; 1389 } __packed; 1390 1391 union hv_msi_entry { /* HV_MSI_ENTRY */ 1392 1393 u64 as_uint64; 1394 struct { 1395 union hv_msi_address_register address; 1396 union hv_msi_data_register data; 1397 } __packed; 1398 }; 1399 1400 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1401 1402 union hv_msi_entry { 1403 u64 as_uint64[2]; 1404 struct { 1405 u64 address; 1406 u32 data; 1407 u32 reserved; 1408 } __packed; 1409 }; 1410 #endif /* CONFIG_ARM64 */ 1411 1412 union hv_ioapic_rte { 1413 u64 as_uint64; 1414 1415 struct { 1416 u32 vector : 8; 1417 u32 delivery_mode : 3; 1418 u32 destination_mode : 1; 1419 u32 delivery_status : 1; 1420 u32 interrupt_polarity : 1; 1421 u32 remote_irr : 1; 1422 u32 trigger_mode : 1; 1423 u32 interrupt_mask : 1; 1424 u32 reserved1 : 15; 1425 1426 u32 reserved2 : 24; 1427 u32 destination_id : 8; 1428 }; 1429 1430 struct { 1431 u32 low_uint32; 1432 u32 high_uint32; 1433 }; 1434 } __packed; 1435 1436 enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */ 1437 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */ 1438 HV_INTERRUPT_SOURCE_IOAPIC, 1439 }; 1440 1441 struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */ 1442 u32 source; 1443 u32 reserved1; 1444 union { 1445 union hv_msi_entry msi_entry; 1446 union hv_ioapic_rte ioapic_rte; 1447 }; 1448 } __packed; 1449 1450 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1 1451 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2 1452 1453 struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */ 1454 u32 vector; 1455 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */ 1456 union { 1457 u64 vp_mask; 1458 struct hv_vpset vp_set; 1459 }; 1460 } __packed; 1461 1462 struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */ 1463 u64 partition_id; /* use "self" */ 1464 u64 device_id; 1465 struct hv_interrupt_entry int_entry; 1466 u64 reserved2; 1467 struct hv_device_interrupt_target int_target; 1468 } __packed __aligned(8); 1469 1470 enum hv_intercept_type { 1471 #if defined(CONFIG_X86) 1472 HV_INTERCEPT_TYPE_X64_IO_PORT = 0x00000000, 1473 HV_INTERCEPT_TYPE_X64_MSR = 0x00000001, 1474 HV_INTERCEPT_TYPE_X64_CPUID = 0x00000002, 1475 #endif 1476 HV_INTERCEPT_TYPE_EXCEPTION = 0x00000003, 1477 /* Used to be HV_INTERCEPT_TYPE_REGISTER */ 1478 HV_INTERCEPT_TYPE_RESERVED0 = 0x00000004, 1479 HV_INTERCEPT_TYPE_MMIO = 0x00000005, 1480 #if defined(CONFIG_X86) 1481 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0x00000006, 1482 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0x00000007, 1483 #endif 1484 HV_INTERCEPT_TYPE_HYPERCALL = 0x00000008, 1485 #if defined(CONFIG_X86) 1486 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0x00000009, 1487 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0x0000000A, 1488 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0x0000000B, 1489 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0x0000000C, 1490 #endif 1491 HV_INTERCEPT_TYPE_MAX, 1492 HV_INTERCEPT_TYPE_INVALID = 0xFFFFFFFF, 1493 }; 1494 1495 union hv_intercept_parameters { 1496 /* HV_INTERCEPT_PARAMETERS is defined to be an 8-byte field. */ 1497 u64 as_uint64; 1498 #if defined(CONFIG_X86) 1499 /* HV_INTERCEPT_TYPE_X64_IO_PORT */ 1500 u16 io_port; 1501 /* HV_INTERCEPT_TYPE_X64_CPUID */ 1502 u32 cpuid_index; 1503 /* HV_INTERCEPT_TYPE_X64_APIC_WRITE */ 1504 u32 apic_write_mask; 1505 /* HV_INTERCEPT_TYPE_EXCEPTION */ 1506 u16 exception_vector; 1507 /* HV_INTERCEPT_TYPE_X64_MSR_INDEX */ 1508 u32 msr_index; 1509 #endif 1510 /* N.B. Other intercept types do not have any parameters. */ 1511 }; 1512 1513 /* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */ 1514 #define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64 1515 1516 struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */ 1517 u64 gpa; 1518 u32 size; 1519 u32 reserved; 1520 } __packed; 1521 1522 struct hv_mmio_read_output { 1523 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1524 } __packed; 1525 1526 struct hv_mmio_write_input { 1527 u64 gpa; 1528 u32 size; 1529 u32 reserved; 1530 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1531 } __packed; 1532 1533 #endif /* _HV_HVGDK_MINI_H */ 1534