1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Type definitions for the Microsoft hypervisor. 4 */ 5 #ifndef _HV_HVGDK_MINI_H 6 #define _HV_HVGDK_MINI_H 7 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 11 struct hv_u128 { 12 u64 low_part; 13 u64 high_part; 14 } __packed; 15 16 /* NOTE: when adding below, update hv_result_to_string() */ 17 #define HV_STATUS_SUCCESS 0x0 18 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 19 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 20 #define HV_STATUS_INVALID_ALIGNMENT 0x4 21 #define HV_STATUS_INVALID_PARAMETER 0x5 22 #define HV_STATUS_ACCESS_DENIED 0x6 23 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 24 #define HV_STATUS_OPERATION_DENIED 0x8 25 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 26 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA 27 #define HV_STATUS_INSUFFICIENT_MEMORY 0xB 28 #define HV_STATUS_INVALID_PARTITION_ID 0xD 29 #define HV_STATUS_INVALID_VP_INDEX 0xE 30 #define HV_STATUS_NOT_FOUND 0x10 31 #define HV_STATUS_INVALID_PORT_ID 0x11 32 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 33 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 34 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 35 #define HV_STATUS_INVALID_VP_STATE 0x15 36 #define HV_STATUS_NO_RESOURCES 0x1D 37 #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 38 #define HV_STATUS_INVALID_LP_INDEX 0x41 39 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 40 #define HV_STATUS_OPERATION_FAILED 0x71 41 #define HV_STATUS_TIME_OUT 0x78 42 #define HV_STATUS_CALL_PENDING 0x79 43 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 44 45 /* 46 * The Hyper-V TimeRefCount register and the TSC 47 * page provide a guest VM clock with 100ns tick rate 48 */ 49 #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) 50 51 #define HV_HYP_PAGE_SHIFT 12 52 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 53 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 54 #define HV_HYP_LARGE_PAGE_SHIFT 21 55 56 #define HV_PARTITION_ID_INVALID ((u64)0) 57 #define HV_PARTITION_ID_SELF ((u64)-1) 58 59 /* Hyper-V specific model specific registers (MSRs) */ 60 61 #if defined(CONFIG_X86) 62 /* HV_X64_SYNTHETIC_MSR */ 63 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 64 #define HV_X64_MSR_HYPERCALL 0x40000001 65 #define HV_X64_MSR_VP_INDEX 0x40000002 66 #define HV_X64_MSR_RESET 0x40000003 67 #define HV_X64_MSR_VP_RUNTIME 0x40000010 68 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 69 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 70 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 71 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 72 73 /* Define the virtual APIC registers */ 74 #define HV_X64_MSR_EOI 0x40000070 75 #define HV_X64_MSR_ICR 0x40000071 76 #define HV_X64_MSR_TPR 0x40000072 77 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 78 79 /* Define synthetic interrupt controller model specific registers. */ 80 #define HV_X64_MSR_SCONTROL 0x40000080 81 #define HV_X64_MSR_SVERSION 0x40000081 82 #define HV_X64_MSR_SIEFP 0x40000082 83 #define HV_X64_MSR_SIMP 0x40000083 84 #define HV_X64_MSR_EOM 0x40000084 85 #define HV_X64_MSR_SIRBP 0x40000085 86 #define HV_X64_MSR_SINT0 0x40000090 87 #define HV_X64_MSR_SINT1 0x40000091 88 #define HV_X64_MSR_SINT2 0x40000092 89 #define HV_X64_MSR_SINT3 0x40000093 90 #define HV_X64_MSR_SINT4 0x40000094 91 #define HV_X64_MSR_SINT5 0x40000095 92 #define HV_X64_MSR_SINT6 0x40000096 93 #define HV_X64_MSR_SINT7 0x40000097 94 #define HV_X64_MSR_SINT8 0x40000098 95 #define HV_X64_MSR_SINT9 0x40000099 96 #define HV_X64_MSR_SINT10 0x4000009A 97 #define HV_X64_MSR_SINT11 0x4000009B 98 #define HV_X64_MSR_SINT12 0x4000009C 99 #define HV_X64_MSR_SINT13 0x4000009D 100 #define HV_X64_MSR_SINT14 0x4000009E 101 #define HV_X64_MSR_SINT15 0x4000009F 102 103 /* Define synthetic interrupt controller model specific registers for nested hypervisor */ 104 #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 105 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 106 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 107 #define HV_X64_MSR_NESTED_SIMP 0x40001083 108 #define HV_X64_MSR_NESTED_EOM 0x40001084 109 #define HV_X64_MSR_NESTED_SINT0 0x40001090 110 111 /* 112 * Synthetic Timer MSRs. Four timers per vcpu. 113 */ 114 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 115 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 116 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 117 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 118 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 119 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 120 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 121 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 122 123 /* Hyper-V guest idle MSR */ 124 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 125 126 /* Hyper-V guest crash notification MSR's */ 127 #define HV_X64_MSR_CRASH_P0 0x40000100 128 #define HV_X64_MSR_CRASH_P1 0x40000101 129 #define HV_X64_MSR_CRASH_P2 0x40000102 130 #define HV_X64_MSR_CRASH_P3 0x40000103 131 #define HV_X64_MSR_CRASH_P4 0x40000104 132 #define HV_X64_MSR_CRASH_CTL 0x40000105 133 134 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 135 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 136 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 137 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 138 139 #define HV_X64_MSR_CRASH_PARAMS \ 140 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 141 142 #define HV_IPI_LOW_VECTOR 0x10 143 #define HV_IPI_HIGH_VECTOR 0xff 144 145 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 146 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 147 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 148 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 149 150 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 151 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 152 153 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 154 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 155 156 /* Number of XMM registers used in hypercall input/output */ 157 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 158 159 struct hv_reenlightenment_control { 160 u64 vector : 8; 161 u64 reserved1 : 8; 162 u64 enabled : 1; 163 u64 reserved2 : 15; 164 u64 target_vp : 32; 165 } __packed; 166 167 struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ 168 u64 inprogress : 1; 169 u64 reserved : 63; 170 } __packed; 171 172 struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ 173 u64 enabled : 1; 174 u64 reserved : 63; 175 } __packed; 176 177 /* TSC emulation after migration */ 178 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 179 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 180 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 181 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 182 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 183 184 #endif /* CONFIG_X86 */ 185 186 struct hv_output_get_partition_id { 187 u64 partition_id; 188 } __packed; 189 190 /* HV_CRASH_CTL_REG_CONTENTS */ 191 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 192 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 193 194 union hv_reference_tsc_msr { 195 u64 as_uint64; 196 struct { 197 u64 enable : 1; 198 u64 reserved : 11; 199 u64 pfn : 52; 200 } __packed; 201 }; 202 203 /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */ 204 #define HV_MAX_SPARSE_VCPU_BANKS (64) 205 /* The number of vCPUs in one sparse bank */ 206 #define HV_VCPUS_PER_SPARSE_BANK (64) 207 208 /* 209 * Some of Hyper-V structs do not use hv_vpset where linux uses them. 210 * 211 * struct hv_vpset is usually used as part of hypercall input. The portion 212 * that counts as "fixed size input header" vs. "variable size input header" 213 * varies per hypercall. See comments at relevant hypercall call sites as to 214 * how the "valid_bank_mask" field should be accounted. 215 */ 216 struct hv_vpset { /* HV_VP_SET */ 217 u64 format; 218 u64 valid_bank_mask; 219 u64 bank_contents[]; 220 } __packed; 221 222 /* 223 * Version info reported by hypervisor 224 * Changed to a union for convenience 225 */ 226 union hv_hypervisor_version_info { 227 struct { 228 u32 build_number; 229 230 u32 minor_version : 16; 231 u32 major_version : 16; 232 233 u32 service_pack; 234 235 u32 service_number : 24; 236 u32 service_branch : 8; 237 }; 238 struct { 239 u32 eax; 240 u32 ebx; 241 u32 ecx; 242 u32 edx; 243 }; 244 }; 245 246 /* HV_CPUID_FUNCTION */ 247 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 248 #define HYPERV_CPUID_INTERFACE 0x40000001 249 #define HYPERV_CPUID_VERSION 0x40000002 250 #define HYPERV_CPUID_FEATURES 0x40000003 251 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 252 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 253 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 254 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 255 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 256 257 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 258 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 259 260 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 261 /* Support for the extended IOAPIC RTE format */ 262 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 263 #define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3) 264 265 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 266 #define HYPERV_CPUID_MIN 0x40000005 267 #define HYPERV_CPUID_MAX 0x4000ffff 268 269 /* 270 * HV_X64_HYPERVISOR_FEATURES (EAX), or 271 * HV_PARTITION_PRIVILEGE_MASK [31-0] 272 */ 273 #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0) 274 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 275 #define HV_MSR_SYNIC_AVAILABLE BIT(2) 276 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 277 #define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4) 278 #define HV_MSR_HYPERCALL_AVAILABLE BIT(5) 279 #define HV_MSR_VP_INDEX_AVAILABLE BIT(6) 280 #define HV_MSR_RESET_AVAILABLE BIT(7) 281 #define HV_MSR_STAT_PAGES_AVAILABLE BIT(8) 282 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 283 #define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10) 284 #define HV_ACCESS_FREQUENCY_MSRS BIT(11) 285 #define HV_ACCESS_REENLIGHTENMENT BIT(13) 286 #define HV_ACCESS_TSC_INVARIANT BIT(15) 287 288 /* 289 * HV_X64_HYPERVISOR_FEATURES (EBX), or 290 * HV_PARTITION_PRIVILEGE_MASK [63-32] 291 */ 292 #define HV_CREATE_PARTITIONS BIT(0) 293 #define HV_ACCESS_PARTITION_ID BIT(1) 294 #define HV_ACCESS_MEMORY_POOL BIT(2) 295 #define HV_ADJUST_MESSAGE_BUFFERS BIT(3) 296 #define HV_POST_MESSAGES BIT(4) 297 #define HV_SIGNAL_EVENTS BIT(5) 298 #define HV_CREATE_PORT BIT(6) 299 #define HV_CONNECT_PORT BIT(7) 300 #define HV_ACCESS_STATS BIT(8) 301 #define HV_DEBUGGING BIT(11) 302 #define HV_CPU_MANAGEMENT BIT(12) 303 #define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20) 304 #define HV_ISOLATION BIT(22) 305 306 #if defined(CONFIG_X86) 307 /* HV_X64_HYPERVISOR_FEATURES (EDX) */ 308 #define HV_X64_MWAIT_AVAILABLE BIT(0) 309 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 310 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 311 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 312 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 313 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 314 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 315 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 316 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 317 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 318 /* 319 * Support for returning hypercall output block via XMM 320 * registers is available 321 */ 322 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 323 /* stimer Direct Mode is available */ 324 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 325 326 /* 327 * Implementation recommendations. Indicates which behaviors the hypervisor 328 * recommends the OS implement for optimal performance. 329 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 330 */ 331 /* HV_X64_ENLIGHTENMENT_INFORMATION */ 332 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 333 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 334 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 335 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 336 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 337 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 338 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 339 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 340 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 341 #define HV_X64_HYPERV_NESTED BIT(12) 342 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 343 #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) 344 345 /* 346 * CPU management features identification. 347 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 348 */ 349 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 350 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 351 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 352 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 353 354 /* 355 * Virtual processor will never share a physical core with another virtual 356 * processor, except for virtual processors that are reported as sibling SMT 357 * threads. 358 */ 359 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 360 361 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 362 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 363 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 364 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 365 366 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 367 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 368 369 /* 370 * This is specific to AMD and specifies that enlightened TLB flush is 371 * supported. If guest opts in to this feature, ASID invalidations only 372 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 373 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 374 * or HvFlushGuestPhysicalAddressList). 375 */ 376 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 377 378 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 379 #define HV_PARAVISOR_PRESENT BIT(0) 380 381 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 382 #define HV_ISOLATION_TYPE GENMASK(3, 0) 383 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 384 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 385 386 /* HYPERV_CPUID_FEATURES.ECX bits. */ 387 #define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9) 388 #define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10) 389 390 enum hv_isolation_type { 391 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ 392 HV_ISOLATION_TYPE_VBS = 1, 393 HV_ISOLATION_TYPE_SNP = 2, 394 HV_ISOLATION_TYPE_TDX = 3 395 }; 396 397 union hv_x64_msr_hypercall_contents { 398 u64 as_uint64; 399 struct { 400 u64 enable : 1; 401 u64 reserved : 11; 402 u64 guest_physical_address : 52; 403 } __packed; 404 }; 405 #endif /* CONFIG_X86 */ 406 407 #if defined(CONFIG_ARM64) 408 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8) 409 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) 410 #endif /* CONFIG_ARM64 */ 411 412 #if defined(CONFIG_X86) 413 #define HV_MAXIMUM_PROCESSORS 2048 414 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 415 #define HV_MAXIMUM_PROCESSORS 320 416 #endif /* CONFIG_ARM64 */ 417 418 #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1) 419 #define HV_VP_INDEX_SELF ((u32)-2) 420 #define HV_ANY_VP ((u32)-1) 421 422 union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ 423 u64 as_uint64; 424 struct { 425 u64 enable : 1; 426 u64 reserved : 11; 427 u64 pfn : 52; 428 } __packed; 429 }; 430 431 /* Declare the various hypercall operations. */ 432 /* HV_CALL_CODE */ 433 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 434 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 435 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 436 #define HVCALL_SEND_IPI 0x000b 437 #define HVCALL_ENABLE_VP_VTL 0x000f 438 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 439 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 440 #define HVCALL_SEND_IPI_EX 0x0015 441 #define HVCALL_CREATE_PARTITION 0x0040 442 #define HVCALL_INITIALIZE_PARTITION 0x0041 443 #define HVCALL_FINALIZE_PARTITION 0x0042 444 #define HVCALL_DELETE_PARTITION 0x0043 445 #define HVCALL_GET_PARTITION_PROPERTY 0x0044 446 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 447 #define HVCALL_GET_PARTITION_ID 0x0046 448 #define HVCALL_DEPOSIT_MEMORY 0x0048 449 #define HVCALL_WITHDRAW_MEMORY 0x0049 450 #define HVCALL_MAP_GPA_PAGES 0x004b 451 #define HVCALL_UNMAP_GPA_PAGES 0x004c 452 #define HVCALL_INSTALL_INTERCEPT 0x004d 453 #define HVCALL_CREATE_VP 0x004e 454 #define HVCALL_DELETE_VP 0x004f 455 #define HVCALL_GET_VP_REGISTERS 0x0050 456 #define HVCALL_SET_VP_REGISTERS 0x0051 457 #define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052 458 #define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056 459 #define HVCALL_DELETE_PORT 0x0058 460 #define HVCALL_DISCONNECT_PORT 0x005b 461 #define HVCALL_POST_MESSAGE 0x005c 462 #define HVCALL_SIGNAL_EVENT 0x005d 463 #define HVCALL_POST_DEBUG_DATA 0x0069 464 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a 465 #define HVCALL_RESET_DEBUG_SESSION 0x006b 466 #define HVCALL_MAP_STATS_PAGE 0x006c 467 #define HVCALL_UNMAP_STATS_PAGE 0x006d 468 #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076 469 #define HVCALL_GET_SYSTEM_PROPERTY 0x007b 470 #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c 471 #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d 472 #define HVCALL_RETARGET_INTERRUPT 0x007e 473 #define HVCALL_NOTIFY_PARTITION_EVENT 0x0087 474 #define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b 475 #define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091 476 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094 477 #define HVCALL_CREATE_PORT 0x0095 478 #define HVCALL_CONNECT_PORT 0x0096 479 #define HVCALL_START_VP 0x0099 480 #define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a 481 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 482 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 483 #define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0 484 #define HVCALL_POST_MESSAGE_DIRECT 0x00c1 485 #define HVCALL_DISPATCH_VP 0x00c2 486 #define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9 487 #define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7 488 #define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8 489 #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db 490 #define HVCALL_MAP_VP_STATE_PAGE 0x00e1 491 #define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2 492 #define HVCALL_GET_VP_STATE 0x00e3 493 #define HVCALL_SET_VP_STATE 0x00e4 494 #define HVCALL_GET_VP_CPUID_VALUES 0x00f4 495 #define HVCALL_GET_PARTITION_PROPERTY_EX 0x0101 496 #define HVCALL_MMIO_READ 0x0106 497 #define HVCALL_MMIO_WRITE 0x0107 498 #define HVCALL_DISABLE_HYP_EX 0x010f 499 #define HVCALL_MAP_STATS_PAGE2 0x0131 500 501 /* HV_HYPERCALL_INPUT */ 502 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 503 #define HV_HYPERCALL_FAST_BIT BIT(16) 504 #define HV_HYPERCALL_VARHEAD_OFFSET 17 505 #define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17) 506 #define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27) 507 #define HV_HYPERCALL_NESTED BIT_ULL(31) 508 #define HV_HYPERCALL_REP_COMP_OFFSET 32 509 #define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32) 510 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 511 #define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44) 512 #define HV_HYPERCALL_REP_START_OFFSET 48 513 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 514 #define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60) 515 #define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \ 516 HV_HYPERCALL_RSVD1_MASK | \ 517 HV_HYPERCALL_RSVD2_MASK) 518 519 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 520 struct hv_guest_mapping_flush { 521 u64 address_space; 522 u64 flags; 523 } __packed; 524 525 /* 526 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 527 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 528 */ 529 #define HV_MAX_FLUSH_PAGES (2048) 530 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0 531 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1 532 533 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 534 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 535 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 536 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 537 538 /* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */ 539 union hv_gpa_page_range { 540 u64 address_space; 541 struct { 542 u64 additional_pages : 11; 543 u64 largepage : 1; 544 u64 basepfn : 52; 545 } page; 546 struct { 547 u64 reserved : 12; 548 u64 page_size : 1; 549 u64 reserved1 : 8; 550 u64 base_large_pfn : 43; 551 }; 552 }; 553 554 /* 555 * All input flush parameters should be in single page. The max flush 556 * count is equal with how many entries of union hv_gpa_page_range can 557 * be populated into the input parameter page. 558 */ 559 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 560 sizeof(union hv_gpa_page_range)) 561 562 struct hv_guest_mapping_flush_list { 563 u64 address_space; 564 u64 flags; 565 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 566 }; 567 568 struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */ 569 u64 address_space; 570 u64 flags; 571 u64 processor_mask; 572 u64 gva_list[]; 573 } __packed; 574 575 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 576 struct hv_tlb_flush_ex { 577 u64 address_space; 578 u64 flags; 579 struct hv_vpset hv_vp_set; 580 u64 gva_list[]; 581 } __packed; 582 583 struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */ 584 volatile u32 tsc_sequence; 585 u32 reserved1; 586 volatile u64 tsc_scale; 587 volatile s64 tsc_offset; 588 } __packed; 589 590 /* Define the number of synthetic interrupt sources. */ 591 #define HV_SYNIC_SINT_COUNT (16) 592 593 /* Define the expected SynIC version. */ 594 #define HV_SYNIC_VERSION_1 (0x1) 595 /* Valid SynIC vectors are 16-255. */ 596 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 597 598 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 599 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 600 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 601 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 602 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 603 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 604 605 /* Hyper-V defined statically assigned SINTs */ 606 #define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000 607 #define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001 608 #define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002 609 #define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005 610 611 /* mshv assigned SINT for doorbell */ 612 #define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX 613 614 enum hv_interrupt_type { 615 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 616 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 617 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 618 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 619 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 620 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 621 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 622 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 623 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 624 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 625 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 626 }; 627 628 /* Define synthetic interrupt source. */ 629 union hv_synic_sint { 630 u64 as_uint64; 631 struct { 632 u64 vector : 8; 633 u64 reserved1 : 8; 634 u64 masked : 1; 635 u64 auto_eoi : 1; 636 u64 polling : 1; 637 u64 as_intercept : 1; 638 u64 proxy : 1; 639 u64 reserved2 : 43; 640 } __packed; 641 }; 642 643 union hv_x64_xsave_xfem_register { 644 u64 as_uint64; 645 struct { 646 u32 low_uint32; 647 u32 high_uint32; 648 } __packed; 649 struct { 650 u64 legacy_x87 : 1; 651 u64 legacy_sse : 1; 652 u64 avx : 1; 653 u64 mpx_bndreg : 1; 654 u64 mpx_bndcsr : 1; 655 u64 avx_512_op_mask : 1; 656 u64 avx_512_zmmhi : 1; 657 u64 avx_512_zmm16_31 : 1; 658 u64 rsvd8_9 : 2; 659 u64 pasid : 1; 660 u64 cet_u : 1; 661 u64 cet_s : 1; 662 u64 rsvd13_16 : 4; 663 u64 xtile_cfg : 1; 664 u64 xtile_data : 1; 665 u64 rsvd19_63 : 45; 666 } __packed; 667 }; 668 669 /* Synthetic timer configuration */ 670 union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */ 671 u64 as_uint64; 672 struct { 673 u64 enable : 1; 674 u64 periodic : 1; 675 u64 lazy : 1; 676 u64 auto_enable : 1; 677 u64 apic_vector : 8; 678 u64 direct_mode : 1; 679 u64 reserved_z0 : 3; 680 u64 sintx : 4; 681 u64 reserved_z1 : 44; 682 } __packed; 683 }; 684 685 /* Define the number of synthetic timers */ 686 #define HV_SYNIC_STIMER_COUNT (4) 687 688 /* Define port identifier type. */ 689 union hv_port_id { 690 u32 asu32; 691 struct { 692 u32 id : 24; 693 u32 reserved : 8; 694 } __packed u; 695 }; 696 697 #define HV_MESSAGE_SIZE (256) 698 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 699 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 700 701 /* Define hypervisor message types. */ 702 enum hv_message_type { 703 HVMSG_NONE = 0x00000000, 704 705 /* Memory access messages. */ 706 HVMSG_UNMAPPED_GPA = 0x80000000, 707 HVMSG_GPA_INTERCEPT = 0x80000001, 708 709 /* Timer notification messages. */ 710 HVMSG_TIMER_EXPIRED = 0x80000010, 711 712 /* Error messages. */ 713 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 714 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 715 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 716 717 /* 718 * Opaque intercept message. The original intercept message is only 719 * accessible from the mapped intercept message page. 720 */ 721 HVMSG_OPAQUE_INTERCEPT = 0x8000003F, 722 723 /* Trace buffer complete messages. */ 724 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 725 726 /* Hypercall intercept */ 727 HVMSG_HYPERCALL_INTERCEPT = 0x80000050, 728 729 /* SynIC intercepts */ 730 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060, 731 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061, 732 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062, 733 734 /* Async call completion intercept */ 735 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070, 736 737 /* Root scheduler messages */ 738 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100, 739 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101, 740 741 /* Platform-specific processor intercept messages. */ 742 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000, 743 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 744 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 745 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 746 HVMSG_X64_APIC_EOI = 0x80010004, 747 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005, 748 HVMSG_X64_IOMMU_PRQ = 0x80010006, 749 HVMSG_X64_HALT = 0x80010007, 750 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008, 751 HVMSG_X64_SIPI_INTERCEPT = 0x80010009, 752 }; 753 754 /* Define the format of the SIMP register */ 755 union hv_synic_simp { 756 u64 as_uint64; 757 struct { 758 u64 simp_enabled : 1; 759 u64 preserved : 11; 760 u64 base_simp_gpa : 52; 761 } __packed; 762 }; 763 764 union hv_message_flags { 765 u8 asu8; 766 struct { 767 u8 msg_pending : 1; 768 u8 reserved : 7; 769 } __packed; 770 }; 771 772 struct hv_message_header { 773 u32 message_type; 774 u8 payload_size; 775 union hv_message_flags message_flags; 776 u8 reserved[2]; 777 union { 778 u64 sender; 779 union hv_port_id port; 780 }; 781 } __packed; 782 783 /* 784 * Message format for notifications delivered via 785 * intercept message(as_intercept=1) 786 */ 787 struct hv_notification_message_payload { 788 u32 sint_index; 789 } __packed; 790 791 struct hv_message { 792 struct hv_message_header header; 793 union { 794 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 795 } u; 796 } __packed; 797 798 /* Define the synthetic interrupt message page layout. */ 799 struct hv_message_page { 800 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 801 } __packed; 802 803 /* Define timer message payload structure. */ 804 struct hv_timer_message_payload { 805 u32 timer_index; 806 u32 reserved; 807 u64 expiration_time; /* When the timer expired */ 808 u64 delivery_time; /* When the message was delivered */ 809 } __packed; 810 811 struct hv_x64_segment_register { 812 u64 base; 813 u32 limit; 814 u16 selector; 815 union { 816 struct { 817 u16 segment_type : 4; 818 u16 non_system_segment : 1; 819 u16 descriptor_privilege_level : 2; 820 u16 present : 1; 821 u16 reserved : 4; 822 u16 available : 1; 823 u16 _long : 1; 824 u16 _default : 1; 825 u16 granularity : 1; 826 } __packed; 827 u16 attributes; 828 }; 829 } __packed; 830 831 struct hv_x64_table_register { 832 u16 pad[3]; 833 u16 limit; 834 u64 base; 835 } __packed; 836 837 #define HV_NORMAL_VTL 0 838 839 union hv_input_vtl { 840 u8 as_uint8; 841 struct { 842 u8 target_vtl : 4; 843 u8 use_target_vtl : 1; 844 u8 reserved_z : 3; 845 }; 846 } __packed; 847 848 struct hv_init_vp_context { 849 u64 rip; 850 u64 rsp; 851 u64 rflags; 852 853 struct hv_x64_segment_register cs; 854 struct hv_x64_segment_register ds; 855 struct hv_x64_segment_register es; 856 struct hv_x64_segment_register fs; 857 struct hv_x64_segment_register gs; 858 struct hv_x64_segment_register ss; 859 struct hv_x64_segment_register tr; 860 struct hv_x64_segment_register ldtr; 861 862 struct hv_x64_table_register idtr; 863 struct hv_x64_table_register gdtr; 864 865 u64 efer; 866 u64 cr0; 867 u64 cr3; 868 u64 cr4; 869 u64 msr_cr_pat; 870 } __packed; 871 872 struct hv_enable_vp_vtl { 873 u64 partition_id; 874 u32 vp_index; 875 union hv_input_vtl target_vtl; 876 u8 mbz0; 877 u16 mbz1; 878 struct hv_init_vp_context vp_context; 879 } __packed; 880 881 struct hv_get_vp_from_apic_id_in { 882 u64 partition_id; 883 union hv_input_vtl target_vtl; 884 u8 res[7]; 885 u32 apic_ids[]; 886 } __packed; 887 888 struct hv_nested_enlightenments_control { 889 struct { 890 u32 directhypercall : 1; 891 u32 reserved : 31; 892 } __packed features; 893 struct { 894 u32 inter_partition_comm : 1; 895 u32 reserved : 31; 896 } __packed hypercall_controls; 897 } __packed; 898 899 /* Define virtual processor assist page structure. */ 900 struct hv_vp_assist_page { 901 u32 apic_assist; 902 u32 reserved1; 903 u32 vtl_entry_reason; 904 u32 vtl_reserved; 905 u64 vtl_ret_x64rax; 906 u64 vtl_ret_x64rcx; 907 struct hv_nested_enlightenments_control nested_control; 908 u8 enlighten_vmentry; 909 u8 reserved2[7]; 910 u64 current_nested_vmcs; 911 u8 synthetic_time_unhalted_timer_expired; 912 u8 reserved3[7]; 913 u8 virtualization_fault_information[40]; 914 u8 reserved4[8]; 915 u8 intercept_message[256]; 916 u8 vtl_ret_actions[256]; 917 } __packed; 918 919 enum hv_register_name { 920 /* Suspend Registers */ 921 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000, 922 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001, 923 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003, 924 925 /* Version - 128-bit result same as CPUID 0x40000002 */ 926 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100, 927 928 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */ 929 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200, 930 HV_REGISTER_FEATURES_INFO = 0x00000201, 931 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202, 932 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203, 933 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204, 934 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205, 935 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206, 936 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207, 937 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208, 938 939 /* Guest Crash Registers */ 940 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210, 941 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211, 942 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212, 943 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213, 944 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214, 945 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215, 946 947 /* Misc */ 948 HV_REGISTER_VP_RUNTIME = 0x00090000, 949 HV_REGISTER_GUEST_OS_ID = 0x00090002, 950 HV_REGISTER_VP_INDEX = 0x00090003, 951 HV_REGISTER_TIME_REF_COUNT = 0x00090004, 952 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007, 953 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013, 954 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014, 955 HV_REGISTER_REFERENCE_TSC = 0x00090017, 956 957 /* Hypervisor-defined Registers (Synic) */ 958 HV_REGISTER_SINT0 = 0x000A0000, 959 HV_REGISTER_SINT1 = 0x000A0001, 960 HV_REGISTER_SINT2 = 0x000A0002, 961 HV_REGISTER_SINT3 = 0x000A0003, 962 HV_REGISTER_SINT4 = 0x000A0004, 963 HV_REGISTER_SINT5 = 0x000A0005, 964 HV_REGISTER_SINT6 = 0x000A0006, 965 HV_REGISTER_SINT7 = 0x000A0007, 966 HV_REGISTER_SINT8 = 0x000A0008, 967 HV_REGISTER_SINT9 = 0x000A0009, 968 HV_REGISTER_SINT10 = 0x000A000A, 969 HV_REGISTER_SINT11 = 0x000A000B, 970 HV_REGISTER_SINT12 = 0x000A000C, 971 HV_REGISTER_SINT13 = 0x000A000D, 972 HV_REGISTER_SINT14 = 0x000A000E, 973 HV_REGISTER_SINT15 = 0x000A000F, 974 HV_REGISTER_SCONTROL = 0x000A0010, 975 HV_REGISTER_SVERSION = 0x000A0011, 976 HV_REGISTER_SIEFP = 0x000A0012, 977 HV_REGISTER_SIMP = 0x000A0013, 978 HV_REGISTER_EOM = 0x000A0014, 979 HV_REGISTER_SIRBP = 0x000A0015, 980 981 HV_REGISTER_NESTED_SINT0 = 0x000A1000, 982 HV_REGISTER_NESTED_SINT1 = 0x000A1001, 983 HV_REGISTER_NESTED_SINT2 = 0x000A1002, 984 HV_REGISTER_NESTED_SINT3 = 0x000A1003, 985 HV_REGISTER_NESTED_SINT4 = 0x000A1004, 986 HV_REGISTER_NESTED_SINT5 = 0x000A1005, 987 HV_REGISTER_NESTED_SINT6 = 0x000A1006, 988 HV_REGISTER_NESTED_SINT7 = 0x000A1007, 989 HV_REGISTER_NESTED_SINT8 = 0x000A1008, 990 HV_REGISTER_NESTED_SINT9 = 0x000A1009, 991 HV_REGISTER_NESTED_SINT10 = 0x000A100A, 992 HV_REGISTER_NESTED_SINT11 = 0x000A100B, 993 HV_REGISTER_NESTED_SINT12 = 0x000A100C, 994 HV_REGISTER_NESTED_SINT13 = 0x000A100D, 995 HV_REGISTER_NESTED_SINT14 = 0x000A100E, 996 HV_REGISTER_NESTED_SINT15 = 0x000A100F, 997 HV_REGISTER_NESTED_SCONTROL = 0x000A1010, 998 HV_REGISTER_NESTED_SVERSION = 0x000A1011, 999 HV_REGISTER_NESTED_SIFP = 0x000A1012, 1000 HV_REGISTER_NESTED_SIPP = 0x000A1013, 1001 HV_REGISTER_NESTED_EOM = 0x000A1014, 1002 HV_REGISTER_NESTED_SIRBP = 0x000a1015, 1003 1004 /* Hypervisor-defined Registers (Synthetic Timers) */ 1005 HV_REGISTER_STIMER0_CONFIG = 0x000B0000, 1006 HV_REGISTER_STIMER0_COUNT = 0x000B0001, 1007 1008 /* VSM */ 1009 HV_REGISTER_VSM_VP_STATUS = 0x000D0003, 1010 }; 1011 1012 /* 1013 * Arch compatibility regs for use with hv_set/get_register 1014 */ 1015 #if defined(CONFIG_X86) 1016 1017 /* 1018 * To support arch-generic code calling hv_set/get_register: 1019 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq 1020 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 1021 */ 1022 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0) 1023 #define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1) 1024 #define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2) 1025 #define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3) 1026 #define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4) 1027 #define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL) 1028 1029 #define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX) 1030 #define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) 1031 #define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) 1032 1033 #define HV_MSR_SINT0 (HV_X64_MSR_SINT0) 1034 #define HV_MSR_SVERSION (HV_X64_MSR_SVERSION) 1035 #define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL) 1036 #define HV_MSR_SIEFP (HV_X64_MSR_SIEFP) 1037 #define HV_MSR_SIMP (HV_X64_MSR_SIMP) 1038 #define HV_MSR_EOM (HV_X64_MSR_EOM) 1039 #define HV_MSR_SIRBP (HV_X64_MSR_SIRBP) 1040 1041 #define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL) 1042 #define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION) 1043 #define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP) 1044 #define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP) 1045 #define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM) 1046 #define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0) 1047 1048 #define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) 1049 #define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) 1050 1051 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1052 1053 #define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0) 1054 #define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1) 1055 #define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2) 1056 #define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3) 1057 #define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4) 1058 #define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL) 1059 1060 #define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX) 1061 #define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) 1062 #define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) 1063 1064 #define HV_MSR_SINT0 (HV_REGISTER_SINT0) 1065 #define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL) 1066 #define HV_MSR_SIEFP (HV_REGISTER_SIEFP) 1067 #define HV_MSR_SIMP (HV_REGISTER_SIMP) 1068 #define HV_MSR_EOM (HV_REGISTER_EOM) 1069 #define HV_MSR_SIRBP (HV_REGISTER_SIRBP) 1070 1071 #define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) 1072 #define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) 1073 1074 #endif /* CONFIG_ARM64 */ 1075 1076 union hv_explicit_suspend_register { 1077 u64 as_uint64; 1078 struct { 1079 u64 suspended : 1; 1080 u64 reserved : 63; 1081 } __packed; 1082 }; 1083 1084 union hv_intercept_suspend_register { 1085 u64 as_uint64; 1086 struct { 1087 u64 suspended : 1; 1088 u64 reserved : 63; 1089 } __packed; 1090 }; 1091 1092 union hv_dispatch_suspend_register { 1093 u64 as_uint64; 1094 struct { 1095 u64 suspended : 1; 1096 u64 reserved : 63; 1097 } __packed; 1098 }; 1099 1100 union hv_arm64_pending_interruption_register { 1101 u64 as_uint64; 1102 struct { 1103 u64 interruption_pending : 1; 1104 u64 interruption_type: 1; 1105 u64 reserved : 30; 1106 u64 error_code : 32; 1107 } __packed; 1108 }; 1109 1110 union hv_arm64_interrupt_state_register { 1111 u64 as_uint64; 1112 struct { 1113 u64 interrupt_shadow : 1; 1114 u64 reserved : 63; 1115 } __packed; 1116 }; 1117 1118 union hv_arm64_pending_synthetic_exception_event { 1119 u64 as_uint64[2]; 1120 struct { 1121 u8 event_pending : 1; 1122 u8 event_type : 3; 1123 u8 reserved : 4; 1124 u8 rsvd[3]; 1125 u32 exception_type; 1126 u64 context; 1127 } __packed; 1128 }; 1129 1130 union hv_x64_interrupt_state_register { 1131 u64 as_uint64; 1132 struct { 1133 u64 interrupt_shadow : 1; 1134 u64 nmi_masked : 1; 1135 u64 reserved : 62; 1136 } __packed; 1137 }; 1138 1139 union hv_x64_pending_interruption_register { 1140 u64 as_uint64; 1141 struct { 1142 u32 interruption_pending : 1; 1143 u32 interruption_type : 3; 1144 u32 deliver_error_code : 1; 1145 u32 instruction_length : 4; 1146 u32 nested_event : 1; 1147 u32 reserved : 6; 1148 u32 interruption_vector : 16; 1149 u32 error_code; 1150 } __packed; 1151 }; 1152 1153 union hv_register_value { 1154 struct hv_u128 reg128; 1155 u64 reg64; 1156 u32 reg32; 1157 u16 reg16; 1158 u8 reg8; 1159 1160 struct hv_x64_segment_register segment; 1161 struct hv_x64_table_register table; 1162 union hv_explicit_suspend_register explicit_suspend; 1163 union hv_intercept_suspend_register intercept_suspend; 1164 union hv_dispatch_suspend_register dispatch_suspend; 1165 #ifdef CONFIG_ARM64 1166 union hv_arm64_interrupt_state_register interrupt_state; 1167 union hv_arm64_pending_interruption_register pending_interruption; 1168 #endif 1169 #ifdef CONFIG_X86 1170 union hv_x64_interrupt_state_register interrupt_state; 1171 union hv_x64_pending_interruption_register pending_interruption; 1172 #endif 1173 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event; 1174 }; 1175 1176 /* NOTE: Linux helper struct - NOT from Hyper-V code. */ 1177 struct hv_output_get_vp_registers { 1178 DECLARE_FLEX_ARRAY(union hv_register_value, values); 1179 }; 1180 1181 #if defined(CONFIG_ARM64) 1182 /* HvGetVpRegisters returns an array of these output elements */ 1183 struct hv_get_vp_registers_output { 1184 union { 1185 struct { 1186 u32 a; 1187 u32 b; 1188 u32 c; 1189 u32 d; 1190 } as32 __packed; 1191 struct { 1192 u64 low; 1193 u64 high; 1194 } as64 __packed; 1195 }; 1196 }; 1197 1198 #endif /* CONFIG_ARM64 */ 1199 1200 struct hv_register_assoc { 1201 u32 name; /* enum hv_register_name */ 1202 u32 reserved1; 1203 u64 reserved2; 1204 union hv_register_value value; 1205 } __packed; 1206 1207 struct hv_input_get_vp_registers { 1208 u64 partition_id; 1209 u32 vp_index; 1210 union hv_input_vtl input_vtl; 1211 u8 rsvd_z8; 1212 u16 rsvd_z16; 1213 u32 names[]; 1214 } __packed; 1215 1216 struct hv_input_set_vp_registers { 1217 u64 partition_id; 1218 u32 vp_index; 1219 union hv_input_vtl input_vtl; 1220 u8 rsvd_z8; 1221 u16 rsvd_z16; 1222 struct hv_register_assoc elements[]; 1223 } __packed; 1224 1225 #define HV_UNMAP_GPA_LARGE_PAGE 0x2 1226 1227 /* HvCallSendSyntheticClusterIpi hypercall */ 1228 struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */ 1229 u32 vector; 1230 u32 reserved; 1231 u64 cpu_mask; 1232 } __packed; 1233 1234 #define HV_VTL_MASK GENMASK(3, 0) 1235 1236 /* Hyper-V memory host visibility */ 1237 enum hv_mem_host_visibility { 1238 VMBUS_PAGE_NOT_VISIBLE = 0, 1239 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 1240 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 1241 }; 1242 1243 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 1244 #define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2) 1245 struct hv_gpa_range_for_visibility { 1246 u64 partition_id; 1247 u32 host_visibility : 2; 1248 u32 reserved0 : 30; 1249 u32 reserved1; 1250 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 1251 } __packed; 1252 1253 #if defined(CONFIG_X86) 1254 union hv_msi_address_register { /* HV_MSI_ADDRESS */ 1255 u32 as_uint32; 1256 struct { 1257 u32 reserved1 : 2; 1258 u32 destination_mode : 1; 1259 u32 redirection_hint : 1; 1260 u32 reserved2 : 8; 1261 u32 destination_id : 8; 1262 u32 msi_base : 12; 1263 }; 1264 } __packed; 1265 1266 union hv_msi_data_register { /* HV_MSI_ENTRY.Data */ 1267 u32 as_uint32; 1268 struct { 1269 u32 vector : 8; 1270 u32 delivery_mode : 3; 1271 u32 reserved1 : 3; 1272 u32 level_assert : 1; 1273 u32 trigger_mode : 1; 1274 u32 reserved2 : 16; 1275 }; 1276 } __packed; 1277 1278 union hv_msi_entry { /* HV_MSI_ENTRY */ 1279 1280 u64 as_uint64; 1281 struct { 1282 union hv_msi_address_register address; 1283 union hv_msi_data_register data; 1284 } __packed; 1285 }; 1286 1287 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1288 1289 union hv_msi_entry { 1290 u64 as_uint64[2]; 1291 struct { 1292 u64 address; 1293 u32 data; 1294 u32 reserved; 1295 } __packed; 1296 }; 1297 #endif /* CONFIG_ARM64 */ 1298 1299 union hv_ioapic_rte { 1300 u64 as_uint64; 1301 1302 struct { 1303 u32 vector : 8; 1304 u32 delivery_mode : 3; 1305 u32 destination_mode : 1; 1306 u32 delivery_status : 1; 1307 u32 interrupt_polarity : 1; 1308 u32 remote_irr : 1; 1309 u32 trigger_mode : 1; 1310 u32 interrupt_mask : 1; 1311 u32 reserved1 : 15; 1312 1313 u32 reserved2 : 24; 1314 u32 destination_id : 8; 1315 }; 1316 1317 struct { 1318 u32 low_uint32; 1319 u32 high_uint32; 1320 }; 1321 } __packed; 1322 1323 enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */ 1324 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */ 1325 HV_INTERRUPT_SOURCE_IOAPIC, 1326 }; 1327 1328 struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */ 1329 u32 source; 1330 u32 reserved1; 1331 union { 1332 union hv_msi_entry msi_entry; 1333 union hv_ioapic_rte ioapic_rte; 1334 }; 1335 } __packed; 1336 1337 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1 1338 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2 1339 1340 struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */ 1341 u32 vector; 1342 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */ 1343 union { 1344 u64 vp_mask; 1345 struct hv_vpset vp_set; 1346 }; 1347 } __packed; 1348 1349 struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */ 1350 u64 partition_id; /* use "self" */ 1351 u64 device_id; 1352 struct hv_interrupt_entry int_entry; 1353 u64 reserved2; 1354 struct hv_device_interrupt_target int_target; 1355 } __packed __aligned(8); 1356 1357 enum hv_intercept_type { 1358 #if defined(CONFIG_X86) 1359 HV_INTERCEPT_TYPE_X64_IO_PORT = 0x00000000, 1360 HV_INTERCEPT_TYPE_X64_MSR = 0x00000001, 1361 HV_INTERCEPT_TYPE_X64_CPUID = 0x00000002, 1362 #endif 1363 HV_INTERCEPT_TYPE_EXCEPTION = 0x00000003, 1364 /* Used to be HV_INTERCEPT_TYPE_REGISTER */ 1365 HV_INTERCEPT_TYPE_RESERVED0 = 0x00000004, 1366 HV_INTERCEPT_TYPE_MMIO = 0x00000005, 1367 #if defined(CONFIG_X86) 1368 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0x00000006, 1369 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0x00000007, 1370 #endif 1371 HV_INTERCEPT_TYPE_HYPERCALL = 0x00000008, 1372 #if defined(CONFIG_X86) 1373 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0x00000009, 1374 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0x0000000A, 1375 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0x0000000B, 1376 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0x0000000C, 1377 #endif 1378 HV_INTERCEPT_TYPE_MAX, 1379 HV_INTERCEPT_TYPE_INVALID = 0xFFFFFFFF, 1380 }; 1381 1382 union hv_intercept_parameters { 1383 /* HV_INTERCEPT_PARAMETERS is defined to be an 8-byte field. */ 1384 u64 as_uint64; 1385 #if defined(CONFIG_X86) 1386 /* HV_INTERCEPT_TYPE_X64_IO_PORT */ 1387 u16 io_port; 1388 /* HV_INTERCEPT_TYPE_X64_CPUID */ 1389 u32 cpuid_index; 1390 /* HV_INTERCEPT_TYPE_X64_APIC_WRITE */ 1391 u32 apic_write_mask; 1392 /* HV_INTERCEPT_TYPE_EXCEPTION */ 1393 u16 exception_vector; 1394 /* HV_INTERCEPT_TYPE_X64_MSR_INDEX */ 1395 u32 msr_index; 1396 #endif 1397 /* N.B. Other intercept types do not have any parameters. */ 1398 }; 1399 1400 /* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */ 1401 #define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64 1402 1403 struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */ 1404 u64 gpa; 1405 u32 size; 1406 u32 reserved; 1407 } __packed; 1408 1409 struct hv_mmio_read_output { 1410 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1411 } __packed; 1412 1413 struct hv_mmio_write_input { 1414 u64 gpa; 1415 u32 size; 1416 u32 reserved; 1417 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1418 } __packed; 1419 1420 #endif /* _HV_HVGDK_MINI_H */ 1421