1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #ifndef __MEDIATEK_LVTS_DT_H 8 #define __MEDIATEK_LVTS_DT_H 9 10 #define MT7987_CPU 0 11 #define MT7987_ETH2P5G 1 12 13 #define MT7988_CPU_0 0 14 #define MT7988_CPU_1 1 15 #define MT7988_ETH2P5G_0 2 16 #define MT7988_ETH2P5G_1 3 17 #define MT7988_TOPS_0 4 18 #define MT7988_TOPS_1 5 19 #define MT7988_ETHWARP_0 6 20 #define MT7988_ETHWARP_1 7 21 22 #define MT8186_LITTLE_CPU0 0 23 #define MT8186_LITTLE_CPU1 1 24 #define MT8186_LITTLE_CPU2 2 25 #define MT8186_CAM 3 26 #define MT8186_BIG_CPU0 4 27 #define MT8186_BIG_CPU1 5 28 #define MT8186_NNA 6 29 #define MT8186_ADSP 7 30 #define MT8186_GPU 8 31 32 #define MT8188_MCU_LITTLE_CPU0 0 33 #define MT8188_MCU_LITTLE_CPU1 1 34 #define MT8188_MCU_LITTLE_CPU2 2 35 #define MT8188_MCU_LITTLE_CPU3 3 36 #define MT8188_MCU_BIG_CPU0 4 37 #define MT8188_MCU_BIG_CPU1 5 38 39 #define MT8188_AP_APU 0 40 #define MT8188_AP_GPU0 1 41 #define MT8188_AP_GPU1 2 42 #define MT8188_AP_ADSP 3 43 #define MT8188_AP_VDO 4 44 #define MT8188_AP_INFRA 5 45 #define MT8188_AP_CAM1 6 46 #define MT8188_AP_CAM2 7 47 48 #define MT8195_MCU_BIG_CPU0 0 49 #define MT8195_MCU_BIG_CPU1 1 50 #define MT8195_MCU_BIG_CPU2 2 51 #define MT8195_MCU_BIG_CPU3 3 52 #define MT8195_MCU_LITTLE_CPU0 4 53 #define MT8195_MCU_LITTLE_CPU1 5 54 #define MT8195_MCU_LITTLE_CPU2 6 55 #define MT8195_MCU_LITTLE_CPU3 7 56 57 #define MT8195_AP_VPU0 8 58 #define MT8195_AP_VPU1 9 59 #define MT8195_AP_GPU0 10 60 #define MT8195_AP_GPU1 11 61 #define MT8195_AP_VDEC 12 62 #define MT8195_AP_IMG 13 63 #define MT8195_AP_INFRA 14 64 #define MT8195_AP_CAM0 15 65 #define MT8195_AP_CAM1 16 66 67 #define MT8192_MCU_BIG_CPU0 0 68 #define MT8192_MCU_BIG_CPU1 1 69 #define MT8192_MCU_BIG_CPU2 2 70 #define MT8192_MCU_BIG_CPU3 3 71 #define MT8192_MCU_LITTLE_CPU0 4 72 #define MT8192_MCU_LITTLE_CPU1 5 73 #define MT8192_MCU_LITTLE_CPU2 6 74 #define MT8192_MCU_LITTLE_CPU3 7 75 76 #define MT8192_AP_VPU0 8 77 #define MT8192_AP_VPU1 9 78 #define MT8192_AP_GPU0 10 79 #define MT8192_AP_GPU1 11 80 #define MT8192_AP_INFRA 12 81 #define MT8192_AP_CAM 13 82 #define MT8192_AP_MD0 14 83 #define MT8192_AP_MD1 15 84 #define MT8192_AP_MD2 16 85 86 #define MT8196_MCU_MEDIUM_CPU6_0 0 87 #define MT8196_MCU_MEDIUM_CPU6_1 1 88 #define MT8196_MCU_DSU2 2 89 #define MT8196_MCU_DSU3 3 90 #define MT8196_MCU_LITTLE_CPU3 4 91 #define MT8196_MCU_LITTLE_CPU0 5 92 #define MT8196_MCU_LITTLE_CPU1 6 93 #define MT8196_MCU_LITTLE_CPU2 7 94 #define MT8196_MCU_MEDIUM_CPU4_0 8 95 #define MT8196_MCU_MEDIUM_CPU4_1 9 96 #define MT8196_MCU_MEDIUM_CPU5_0 10 97 #define MT8196_MCU_MEDIUM_CPU5_1 11 98 #define MT8196_MCU_DSU0 12 99 #define MT8196_MCU_DSU1 13 100 #define MT8196_MCU_BIG_CPU7_0 14 101 #define MT8196_MCU_BIG_CPU7_1 15 102 103 #define MT8196_AP_TOP0 0 104 #define MT8196_AP_TOP1 1 105 #define MT8196_AP_TOP2 2 106 #define MT8196_AP_TOP3 3 107 #define MT8196_AP_BOT0 4 108 #define MT8196_AP_BOT1 5 109 #define MT8196_AP_BOT2 6 110 #define MT8196_AP_BOT3 7 111 112 #endif /* __MEDIATEK_LVTS_DT_H */ 113