163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 2d06a171eSVidya Sagar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H 563944891SThierry Reding #define DT_BINDINGS_RESET_TEGRA234_RESET_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_reset_ids Reset ID's 10fc5e0e37SMikko Perttunen * @brief Identifiers for Resets controllable by firmware 11fc5e0e37SMikko Perttunen * @{ 12fc5e0e37SMikko Perttunen */ 13d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_6 11U 14d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_6_APB 12U 15d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_COMMON_APB 13U 16d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_7 14U 17d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_7_APB 15U 18*3ffb20f5SAkhil R #define TEGRA234_RESET_GPCDMA 18U 1907d74390SMohan Kumar #define TEGRA234_RESET_HDA 20U 2007d74390SMohan Kumar #define TEGRA234_RESET_HDACODEC 21U 21bb747becSAkhil R #define TEGRA234_RESET_I2C1 24U 22d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_8 25U 23d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_8_APB 26U 24d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_9 27U 25d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_9_APB 28U 26bb747becSAkhil R #define TEGRA234_RESET_I2C2 29U 27bb747becSAkhil R #define TEGRA234_RESET_I2C3 30U 28bb747becSAkhil R #define TEGRA234_RESET_I2C4 31U 29bb747becSAkhil R #define TEGRA234_RESET_I2C6 32U 30bb747becSAkhil R #define TEGRA234_RESET_I2C7 33U 31bb747becSAkhil R #define TEGRA234_RESET_I2C8 34U 32bb747becSAkhil R #define TEGRA234_RESET_I2C9 35U 33d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_10 56U 34d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_10_APB 57U 35d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_COMMON_APB 58U 3638eb21a5SAkhil R #define TEGRA234_RESET_PWM1 68U 3738eb21a5SAkhil R #define TEGRA234_RESET_PWM2 69U 3838eb21a5SAkhil R #define TEGRA234_RESET_PWM3 70U 3938eb21a5SAkhil R #define TEGRA234_RESET_PWM4 71U 4038eb21a5SAkhil R #define TEGRA234_RESET_PWM5 72U 4138eb21a5SAkhil R #define TEGRA234_RESET_PWM6 73U 4238eb21a5SAkhil R #define TEGRA234_RESET_PWM7 74U 4338eb21a5SAkhil R #define TEGRA234_RESET_PWM8 75U 4471f69ffaSAshish Singhal #define TEGRA234_RESET_QSPI0 76U 4571f69ffaSAshish Singhal #define TEGRA234_RESET_QSPI1 77U 46fc5e0e37SMikko Perttunen #define TEGRA234_RESET_SDMMC4 85U 47fc5e0e37SMikko Perttunen #define TEGRA234_RESET_UARTA 100U 48d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_0 116U 49d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_1 117U 50d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_2 118U 51d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_3 119U 52d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_4 120U 53d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_0_APB 121U 54d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_1_APB 122U 55d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_2_APB 123U 56d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_3_APB 124U 57d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_4_APB 125U 58d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_COMMON_APB 126U 59d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_5 129U 60d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_5_APB 130U 61fc5e0e37SMikko Perttunen 62fc5e0e37SMikko Perttunen /** @} */ 6363944891SThierry Reding 6463944891SThierry Reding #endif 65