xref: /linux/include/dt-bindings/reset/tegra234-reset.h (revision 0e2b014eeb257173c72014ebd02ab0d60643f0f8)
163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */
2d06a171eSVidya Sagar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
363944891SThierry Reding 
463944891SThierry Reding #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
563944891SThierry Reding #define DT_BINDINGS_RESET_TEGRA234_RESET_H
663944891SThierry Reding 
7fc5e0e37SMikko Perttunen /**
8fc5e0e37SMikko Perttunen  * @file
9fc5e0e37SMikko Perttunen  * @defgroup bpmp_reset_ids Reset ID's
10fc5e0e37SMikko Perttunen  * @brief Identifiers for Resets controllable by firmware
11fc5e0e37SMikko Perttunen  * @{
12fc5e0e37SMikko Perttunen  */
13d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_6		11U
14d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_6_APB		12U
15d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_COMMON_APB		13U
16d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_7		14U
17d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_7_APB		15U
183ffb20f5SAkhil R #define TEGRA234_RESET_GPCDMA			18U
1907d74390SMohan Kumar #define TEGRA234_RESET_HDA			20U
2007d74390SMohan Kumar #define TEGRA234_RESET_HDACODEC			21U
21bb747becSAkhil R #define TEGRA234_RESET_I2C1			24U
22d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_8		25U
23d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_8_APB		26U
24d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_9		27U
25d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_9_APB		28U
26bb747becSAkhil R #define TEGRA234_RESET_I2C2			29U
27bb747becSAkhil R #define TEGRA234_RESET_I2C3			30U
28bb747becSAkhil R #define TEGRA234_RESET_I2C4			31U
29bb747becSAkhil R #define TEGRA234_RESET_I2C6			32U
30bb747becSAkhil R #define TEGRA234_RESET_I2C7			33U
31bb747becSAkhil R #define TEGRA234_RESET_I2C8			34U
32bb747becSAkhil R #define TEGRA234_RESET_I2C9			35U
33*0e2b014eSMikko Perttunen #define TEGRA234_RESET_NVDEC			44U
34b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE0_PCS		45U
35b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE0_MAC		46U
36b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE1_PCS		49U
37b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE1_MAC		50U
38b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE2_PCS		53U
39b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE2_MAC		54U
40d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_10		56U
41d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_CORE_10_APB		57U
42d06a171eSVidya Sagar #define TEGRA234_RESET_PEX2_COMMON_APB		58U
4338eb21a5SAkhil R #define TEGRA234_RESET_PWM1			68U
4438eb21a5SAkhil R #define TEGRA234_RESET_PWM2			69U
4538eb21a5SAkhil R #define TEGRA234_RESET_PWM3			70U
4638eb21a5SAkhil R #define TEGRA234_RESET_PWM4			71U
4738eb21a5SAkhil R #define TEGRA234_RESET_PWM5			72U
4838eb21a5SAkhil R #define TEGRA234_RESET_PWM6			73U
4938eb21a5SAkhil R #define TEGRA234_RESET_PWM7			74U
5038eb21a5SAkhil R #define TEGRA234_RESET_PWM8			75U
5171f69ffaSAshish Singhal #define TEGRA234_RESET_QSPI0			76U
5271f69ffaSAshish Singhal #define TEGRA234_RESET_QSPI1			77U
53fc5e0e37SMikko Perttunen #define TEGRA234_RESET_SDMMC4			85U
54b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE3_PCS		87U
55b0aedf34SThierry Reding #define TEGRA234_RESET_MGBE3_MAC		88U
56fc5e0e37SMikko Perttunen #define TEGRA234_RESET_UARTA			100U
5763a6ef23SMikko Perttunen #define TEGRA234_RESET_VIC                      113U
58d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_0		116U
59d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_1		117U
60d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_2		118U
61d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_3		119U
62d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_4		120U
63d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_0_APB		121U
64d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_1_APB		122U
65d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_2_APB		123U
66d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_3_APB		124U
67d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_CORE_4_APB		125U
68d06a171eSVidya Sagar #define TEGRA234_RESET_PEX0_COMMON_APB		126U
69d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_5		129U
70d06a171eSVidya Sagar #define TEGRA234_RESET_PEX1_CORE_5_APB		130U
71fc5e0e37SMikko Perttunen 
72fc5e0e37SMikko Perttunen /** @} */
7363944891SThierry Reding 
7463944891SThierry Reding #endif
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