xref: /linux/include/dt-bindings/reset/tegra234-reset.h (revision 07d743902a1205d54d93c0637c22575811014431)
163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */
263944891SThierry Reding /* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */
363944891SThierry Reding 
463944891SThierry Reding #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
563944891SThierry Reding #define DT_BINDINGS_RESET_TEGRA234_RESET_H
663944891SThierry Reding 
7fc5e0e37SMikko Perttunen /**
8fc5e0e37SMikko Perttunen  * @file
9fc5e0e37SMikko Perttunen  * @defgroup bpmp_reset_ids Reset ID's
10fc5e0e37SMikko Perttunen  * @brief Identifiers for Resets controllable by firmware
11fc5e0e37SMikko Perttunen  * @{
12fc5e0e37SMikko Perttunen  */
13*07d74390SMohan Kumar #define TEGRA234_RESET_HDA			20U
14*07d74390SMohan Kumar #define TEGRA234_RESET_HDACODEC			21U
15bb747becSAkhil R #define TEGRA234_RESET_I2C1			24U
16bb747becSAkhil R #define TEGRA234_RESET_I2C2			29U
17bb747becSAkhil R #define TEGRA234_RESET_I2C3			30U
18bb747becSAkhil R #define TEGRA234_RESET_I2C4			31U
19bb747becSAkhil R #define TEGRA234_RESET_I2C6			32U
20bb747becSAkhil R #define TEGRA234_RESET_I2C7			33U
21bb747becSAkhil R #define TEGRA234_RESET_I2C8			34U
22bb747becSAkhil R #define TEGRA234_RESET_I2C9			35U
2338eb21a5SAkhil R #define TEGRA234_RESET_PWM1			68U
2438eb21a5SAkhil R #define TEGRA234_RESET_PWM2			69U
2538eb21a5SAkhil R #define TEGRA234_RESET_PWM3			70U
2638eb21a5SAkhil R #define TEGRA234_RESET_PWM4			71U
2738eb21a5SAkhil R #define TEGRA234_RESET_PWM5			72U
2838eb21a5SAkhil R #define TEGRA234_RESET_PWM6			73U
2938eb21a5SAkhil R #define TEGRA234_RESET_PWM7			74U
3038eb21a5SAkhil R #define TEGRA234_RESET_PWM8			75U
31fc5e0e37SMikko Perttunen #define TEGRA234_RESET_SDMMC4			85U
32fc5e0e37SMikko Perttunen #define TEGRA234_RESET_UARTA			100U
33fc5e0e37SMikko Perttunen 
34fc5e0e37SMikko Perttunen /** @} */
3563944891SThierry Reding 
3663944891SThierry Reding #endif
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