1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ 7 #define _DT_BINDINGS_RESET_SUN50I_H6_H_ 8 9 #define RST_MBUS 0 10 #define RST_BUS_DE 1 11 #define RST_BUS_DEINTERLACE 2 12 #define RST_BUS_GPU 3 13 #define RST_BUS_CE 4 14 #define RST_BUS_VE 5 15 #define RST_BUS_EMCE 6 16 #define RST_BUS_VP9 7 17 #define RST_BUS_DMA 8 18 #define RST_BUS_MSGBOX 9 19 #define RST_BUS_SPINLOCK 10 20 #define RST_BUS_HSTIMER 11 21 #define RST_BUS_DBG 12 22 #define RST_BUS_PSI 13 23 #define RST_BUS_PWM 14 24 #define RST_BUS_IOMMU 15 25 #define RST_BUS_DRAM 16 26 #define RST_BUS_NAND 17 27 #define RST_BUS_MMC0 18 28 #define RST_BUS_MMC1 19 29 #define RST_BUS_MMC2 20 30 #define RST_BUS_UART0 21 31 #define RST_BUS_UART1 22 32 #define RST_BUS_UART2 23 33 #define RST_BUS_UART3 24 34 #define RST_BUS_I2C0 25 35 #define RST_BUS_I2C1 26 36 #define RST_BUS_I2C2 27 37 #define RST_BUS_I2C3 28 38 #define RST_BUS_SCR0 29 39 #define RST_BUS_SCR1 30 40 #define RST_BUS_SPI0 31 41 #define RST_BUS_SPI1 32 42 #define RST_BUS_EMAC 33 43 #define RST_BUS_TS 34 44 #define RST_BUS_IR_TX 35 45 #define RST_BUS_THS 36 46 #define RST_BUS_I2S0 37 47 #define RST_BUS_I2S1 38 48 #define RST_BUS_I2S2 39 49 #define RST_BUS_I2S3 40 50 #define RST_BUS_SPDIF 41 51 #define RST_BUS_DMIC 42 52 #define RST_BUS_AUDIO_HUB 43 53 #define RST_USB_PHY0 44 54 #define RST_USB_PHY1 45 55 #define RST_USB_PHY3 46 56 #define RST_USB_HSIC 47 57 #define RST_BUS_OHCI0 48 58 #define RST_BUS_OHCI3 49 59 #define RST_BUS_EHCI0 50 60 #define RST_BUS_XHCI 51 61 #define RST_BUS_EHCI3 52 62 #define RST_BUS_OTG 53 63 #define RST_BUS_PCIE 54 64 #define RST_PCIE_POWERUP 55 65 #define RST_BUS_HDMI 56 66 #define RST_BUS_HDMI_SUB 57 67 #define RST_BUS_TCON_TOP 58 68 #define RST_BUS_TCON_LCD0 59 69 #define RST_BUS_TCON_TV0 60 70 #define RST_BUS_CSI 61 71 #define RST_BUS_HDCP 62 72 73 #endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ 74