1*63313c1cSAndreas Färber /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 2*63313c1cSAndreas Färber /* 3*63313c1cSAndreas Färber * Realtek RTD1195 reset controllers 4*63313c1cSAndreas Färber * 5*63313c1cSAndreas Färber * Copyright (c) 2017 Andreas Färber 6*63313c1cSAndreas Färber */ 7*63313c1cSAndreas Färber #ifndef DT_BINDINGS_RESET_RTD1195_H 8*63313c1cSAndreas Färber #define DT_BINDINGS_RESET_RTD1195_H 9*63313c1cSAndreas Färber 10*63313c1cSAndreas Färber /* soft reset 1 */ 11*63313c1cSAndreas Färber #define RTD1195_RSTN_MISC 0 12*63313c1cSAndreas Färber #define RTD1195_RSTN_RNG 1 13*63313c1cSAndreas Färber #define RTD1195_RSTN_USB3_POW 2 14*63313c1cSAndreas Färber #define RTD1195_RSTN_GSPI 3 15*63313c1cSAndreas Färber #define RTD1195_RSTN_USB3_P0_MDIO 4 16*63313c1cSAndreas Färber #define RTD1195_RSTN_VE_H265 5 17*63313c1cSAndreas Färber #define RTD1195_RSTN_USB 6 18*63313c1cSAndreas Färber #define RTD1195_RSTN_USB_PHY0 8 19*63313c1cSAndreas Färber #define RTD1195_RSTN_USB_PHY1 9 20*63313c1cSAndreas Färber #define RTD1195_RSTN_HDMIRX 11 21*63313c1cSAndreas Färber #define RTD1195_RSTN_HDMI 12 22*63313c1cSAndreas Färber #define RTD1195_RSTN_ETN 14 23*63313c1cSAndreas Färber #define RTD1195_RSTN_AIO 15 24*63313c1cSAndreas Färber #define RTD1195_RSTN_GPU 16 25*63313c1cSAndreas Färber #define RTD1195_RSTN_VE_H264 17 26*63313c1cSAndreas Färber #define RTD1195_RSTN_VE_JPEG 18 27*63313c1cSAndreas Färber #define RTD1195_RSTN_TVE 19 28*63313c1cSAndreas Färber #define RTD1195_RSTN_VO 20 29*63313c1cSAndreas Färber #define RTD1195_RSTN_LVDS 21 30*63313c1cSAndreas Färber #define RTD1195_RSTN_SE 22 31*63313c1cSAndreas Färber #define RTD1195_RSTN_DCU 23 32*63313c1cSAndreas Färber #define RTD1195_RSTN_DC_PHY 24 33*63313c1cSAndreas Färber #define RTD1195_RSTN_CP 25 34*63313c1cSAndreas Färber #define RTD1195_RSTN_MD 26 35*63313c1cSAndreas Färber #define RTD1195_RSTN_TP 27 36*63313c1cSAndreas Färber #define RTD1195_RSTN_AE 28 37*63313c1cSAndreas Färber #define RTD1195_RSTN_NF 29 38*63313c1cSAndreas Färber #define RTD1195_RSTN_MIPI 30 39*63313c1cSAndreas Färber 40*63313c1cSAndreas Färber /* soft reset 2 */ 41*63313c1cSAndreas Färber #define RTD1195_RSTN_ACPU 0 42*63313c1cSAndreas Färber #define RTD1195_RSTN_VCPU 1 43*63313c1cSAndreas Färber #define RTD1195_RSTN_PCR 9 44*63313c1cSAndreas Färber #define RTD1195_RSTN_CR 10 45*63313c1cSAndreas Färber #define RTD1195_RSTN_EMMC 11 46*63313c1cSAndreas Färber #define RTD1195_RSTN_SDIO 12 47*63313c1cSAndreas Färber #define RTD1195_RSTN_I2C_5 18 48*63313c1cSAndreas Färber #define RTD1195_RSTN_RTC 20 49*63313c1cSAndreas Färber #define RTD1195_RSTN_I2C_4 23 50*63313c1cSAndreas Färber #define RTD1195_RSTN_I2C_3 24 51*63313c1cSAndreas Färber #define RTD1195_RSTN_I2C_2 25 52*63313c1cSAndreas Färber #define RTD1195_RSTN_I2C_1 26 53*63313c1cSAndreas Färber #define RTD1195_RSTN_UR1 28 54*63313c1cSAndreas Färber 55*63313c1cSAndreas Färber /* soft reset 3 */ 56*63313c1cSAndreas Färber #define RTD1195_RSTN_SB2 0 57*63313c1cSAndreas Färber 58*63313c1cSAndreas Färber /* iso soft reset */ 59*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_VFD 0 60*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_IR 1 61*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CEC0 2 62*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CEC1 3 63*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_DP 4 64*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CBUSTX 5 65*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CBUSRX 6 66*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_EFUSE 7 67*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_UR0 8 68*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_GMAC 9 69*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_GPHY 10 70*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_I2C_0 11 71*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_I2C_6 12 72*63313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CBUS 13 73*63313c1cSAndreas Färber 74*63313c1cSAndreas Färber #endif 75