1*ea1cca02SYassine Oudjana /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ea1cca02SYassine Oudjana 3*ea1cca02SYassine Oudjana #ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H 4*ea1cca02SYassine Oudjana #define _DT_BINDINGS_RESET_MT6735_INFRACFG_H 5*ea1cca02SYassine Oudjana 6*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_EMI_REG 0 7*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_DRAMC0_AO 1 8*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_AP_CIRQ_EINT 2 9*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_APXGPT 3 10*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_SCPSYS 4 11*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_KP 5 12*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_PMIC_WRAP 6 13*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_CLDMA_AO_TOP 7 14*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_USBSIF_TOP 8 15*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_EMI 9 16*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_CCIF 10 17*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_DRAMC0 11 18*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_EMI_AO_REG 12 19*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_CCIF_AO 13 20*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_TRNG 14 21*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_SYS_CIRQ 15 22*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_GCE 16 23*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_M4U 17 24*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_CCIF1 18 25*ea1cca02SYassine Oudjana #define MT6735_INFRA_RST0_CLDMA_TOP_PD 19 26*ea1cca02SYassine Oudjana 27*ea1cca02SYassine Oudjana #endif 28