1*ea1cca02SYassine Oudjana /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ea1cca02SYassine Oudjana 3*ea1cca02SYassine Oudjana #ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H 4*ea1cca02SYassine Oudjana #define _DT_BINDINGS_RESET_MT6735_PERICFG_H 5*ea1cca02SYassine Oudjana 6*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_UART0 0 7*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_UART1 1 8*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_UART2 2 9*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_UART3 3 10*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_UART4 4 11*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_BTIF 5 12*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_DISP_PWM_PERI 6 13*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_PWM 7 14*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_AUXADC 8 15*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_DMA 9 16*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_IRDA 10 17*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_IRTX 11 18*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_THERM 12 19*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_MSDC2 13 20*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_MSDC3 14 21*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_MSDC0 15 22*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_MSDC1 16 23*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_I2C0 17 24*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_I2C1 18 25*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_I2C2 19 26*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_I2C3 20 27*ea1cca02SYassine Oudjana #define MT6735_PERI_RST0_USB 21 28*ea1cca02SYassine Oudjana 29*ea1cca02SYassine Oudjana #define MT6735_PERI_RST1_SPI0 22 30*ea1cca02SYassine Oudjana 31*ea1cca02SYassine Oudjana #endif 32