1*04d11269SChen Feng /** 2*04d11269SChen Feng * This header provides index for the reset controller 3*04d11269SChen Feng * based on hi6220 SoC. 4*04d11269SChen Feng */ 5*04d11269SChen Feng #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 6*04d11269SChen Feng #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 7*04d11269SChen Feng 8*04d11269SChen Feng #define PERIPH_RSTDIS0_MMC0 0x000 9*04d11269SChen Feng #define PERIPH_RSTDIS0_MMC1 0x001 10*04d11269SChen Feng #define PERIPH_RSTDIS0_MMC2 0x002 11*04d11269SChen Feng #define PERIPH_RSTDIS0_NANDC 0x003 12*04d11269SChen Feng #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 13*04d11269SChen Feng #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 14*04d11269SChen Feng #define PERIPH_RSTDIS0_USBOTG 0x006 15*04d11269SChen Feng #define PERIPH_RSTDIS0_USBOTG_32K 0x007 16*04d11269SChen Feng #define PERIPH_RSTDIS1_HIFI 0x100 17*04d11269SChen Feng #define PERIPH_RSTDIS1_DIGACODEC 0x105 18*04d11269SChen Feng #define PERIPH_RSTEN2_IPF 0x200 19*04d11269SChen Feng #define PERIPH_RSTEN2_SOCP 0x201 20*04d11269SChen Feng #define PERIPH_RSTEN2_DMAC 0x202 21*04d11269SChen Feng #define PERIPH_RSTEN2_SECENG 0x203 22*04d11269SChen Feng #define PERIPH_RSTEN2_ABB 0x204 23*04d11269SChen Feng #define PERIPH_RSTEN2_HPM0 0x205 24*04d11269SChen Feng #define PERIPH_RSTEN2_HPM1 0x206 25*04d11269SChen Feng #define PERIPH_RSTEN2_HPM2 0x207 26*04d11269SChen Feng #define PERIPH_RSTEN2_HPM3 0x208 27*04d11269SChen Feng #define PERIPH_RSTEN3_CSSYS 0x300 28*04d11269SChen Feng #define PERIPH_RSTEN3_I2C0 0x301 29*04d11269SChen Feng #define PERIPH_RSTEN3_I2C1 0x302 30*04d11269SChen Feng #define PERIPH_RSTEN3_I2C2 0x303 31*04d11269SChen Feng #define PERIPH_RSTEN3_I2C3 0x304 32*04d11269SChen Feng #define PERIPH_RSTEN3_UART1 0x305 33*04d11269SChen Feng #define PERIPH_RSTEN3_UART2 0x306 34*04d11269SChen Feng #define PERIPH_RSTEN3_UART3 0x307 35*04d11269SChen Feng #define PERIPH_RSTEN3_UART4 0x308 36*04d11269SChen Feng #define PERIPH_RSTEN3_SSP 0x309 37*04d11269SChen Feng #define PERIPH_RSTEN3_PWM 0x30a 38*04d11269SChen Feng #define PERIPH_RSTEN3_BLPWM 0x30b 39*04d11269SChen Feng #define PERIPH_RSTEN3_TSENSOR 0x30c 40*04d11269SChen Feng #define PERIPH_RSTEN3_DAPB 0x312 41*04d11269SChen Feng #define PERIPH_RSTEN3_HKADC 0x313 42*04d11269SChen Feng #define PERIPH_RSTEN3_CODEC_SSI 0x314 43*04d11269SChen Feng #define PERIPH_RSTEN3_PMUSSI1 0x316 44*04d11269SChen Feng #define PERIPH_RSTEN8_RS0 0x400 45*04d11269SChen Feng #define PERIPH_RSTEN8_RS2 0x401 46*04d11269SChen Feng #define PERIPH_RSTEN8_RS3 0x402 47*04d11269SChen Feng #define PERIPH_RSTEN8_MS0 0x403 48*04d11269SChen Feng #define PERIPH_RSTEN8_MS2 0x405 49*04d11269SChen Feng #define PERIPH_RSTEN8_XG2RAM0 0x406 50*04d11269SChen Feng #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 51*04d11269SChen Feng #define PERIPH_RSTEN8_SRAM 0x408 52*04d11269SChen Feng #define PERIPH_RSTEN8_HARQ 0x40a 53*04d11269SChen Feng #define PERIPH_RSTEN8_DDRC 0x40c 54*04d11269SChen Feng #define PERIPH_RSTEN8_DDRC_APB 0x40d 55*04d11269SChen Feng #define PERIPH_RSTEN8_DDRPACK_APB 0x40e 56*04d11269SChen Feng #define PERIPH_RSTEN8_DDRT 0x411 57*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_DAP 0x500 58*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_ATB 0x501 59*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_LBUS 0x502 60*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_POR 0x503 61*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_CORE 0x504 62*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_DBG 0x505 63*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_L2 0x506 64*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 65*04d11269SChen Feng #define PERIPH_RSDIST9_CARM_ETM 0x508 66*04d11269SChen Feng 67*04d11269SChen Feng #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 68