1*3b521bf8SLaurentiu Mihalcea /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*3b521bf8SLaurentiu Mihalcea /* 3*3b521bf8SLaurentiu Mihalcea * Copyright 2025 NXP 4*3b521bf8SLaurentiu Mihalcea */ 5*3b521bf8SLaurentiu Mihalcea 6*3b521bf8SLaurentiu Mihalcea #ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H 7*3b521bf8SLaurentiu Mihalcea #define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H 8*3b521bf8SLaurentiu Mihalcea 9*3b521bf8SLaurentiu Mihalcea #define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST 0 10*3b521bf8SLaurentiu Mihalcea #define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST 1 11*3b521bf8SLaurentiu Mihalcea #define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL 2 12*3b521bf8SLaurentiu Mihalcea #define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N 3 13*3b521bf8SLaurentiu Mihalcea #define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N 4 14*3b521bf8SLaurentiu Mihalcea #define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N 5 15*3b521bf8SLaurentiu Mihalcea 16*3b521bf8SLaurentiu Mihalcea #endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */ 17