1*11ea09b9SSerge Semin /* SPDX-License-Identifier: GPL-2.0-only */ 2*11ea09b9SSerge Semin /* 3*11ea09b9SSerge Semin * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4*11ea09b9SSerge Semin * 5*11ea09b9SSerge Semin * Baikal-T1 CCU reset indices 6*11ea09b9SSerge Semin */ 7*11ea09b9SSerge Semin #ifndef __DT_BINDINGS_RESET_BT1_CCU_H 8*11ea09b9SSerge Semin #define __DT_BINDINGS_RESET_BT1_CCU_H 9*11ea09b9SSerge Semin 10*11ea09b9SSerge Semin #define CCU_AXI_MAIN_RST 0 11*11ea09b9SSerge Semin #define CCU_AXI_DDR_RST 1 12*11ea09b9SSerge Semin #define CCU_AXI_SATA_RST 2 13*11ea09b9SSerge Semin #define CCU_AXI_GMAC0_RST 3 14*11ea09b9SSerge Semin #define CCU_AXI_GMAC1_RST 4 15*11ea09b9SSerge Semin #define CCU_AXI_XGMAC_RST 5 16*11ea09b9SSerge Semin #define CCU_AXI_PCIE_M_RST 6 17*11ea09b9SSerge Semin #define CCU_AXI_PCIE_S_RST 7 18*11ea09b9SSerge Semin #define CCU_AXI_USB_RST 8 19*11ea09b9SSerge Semin #define CCU_AXI_HWA_RST 9 20*11ea09b9SSerge Semin #define CCU_AXI_SRAM_RST 10 21*11ea09b9SSerge Semin 22*11ea09b9SSerge Semin #define CCU_SYS_SATA_REF_RST 0 23*11ea09b9SSerge Semin #define CCU_SYS_APB_RST 1 24*11ea09b9SSerge Semin 25*11ea09b9SSerge Semin #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ 26