1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Device Tree binding constants for AST2700 reset controller. 4 * 5 * Copyright (c) 2024 Aspeed Technology Inc. 6 */ 7 8 #ifndef _MACH_ASPEED_AST2700_RESET_H_ 9 #define _MACH_ASPEED_AST2700_RESET_H_ 10 11 /* SOC0 */ 12 #define SCU0_RESET_SDRAM 0 13 #define SCU0_RESET_DDRPHY 1 14 #define SCU0_RESET_RSA 2 15 #define SCU0_RESET_SHA3 3 16 #define SCU0_RESET_HACE 4 17 #define SCU0_RESET_SOC 5 18 #define SCU0_RESET_VIDEO 6 19 #define SCU0_RESET_2D 7 20 #define SCU0_RESET_PCIS 8 21 #define SCU0_RESET_RVAS0 9 22 #define SCU0_RESET_RVAS1 10 23 #define SCU0_RESET_SM3 11 24 #define SCU0_RESET_SM4 12 25 #define SCU0_RESET_CRT0 13 26 #define SCU0_RESET_ECC 14 27 #define SCU0_RESET_DP_PCI 15 28 #define SCU0_RESET_UFS 16 29 #define SCU0_RESET_EMMC 17 30 #define SCU0_RESET_PCIE1RST 18 31 #define SCU0_RESET_PCIE1RSTOE 19 32 #define SCU0_RESET_PCIE0RST 20 33 #define SCU0_RESET_PCIE0RSTOE 21 34 #define SCU0_RESET_JTAG 22 35 #define SCU0_RESET_MCTP0 23 36 #define SCU0_RESET_MCTP1 24 37 #define SCU0_RESET_XDMA0 25 38 #define SCU0_RESET_XDMA1 26 39 #define SCU0_RESET_H2X1 27 40 #define SCU0_RESET_DP 28 41 #define SCU0_RESET_DP_MCU 29 42 #define SCU0_RESET_SSP 30 43 #define SCU0_RESET_H2X0 31 44 #define SCU0_RESET_PORTA_VHUB 32 45 #define SCU0_RESET_PORTA_PHY3 33 46 #define SCU0_RESET_PORTA_XHCI 34 47 #define SCU0_RESET_PORTB_VHUB 35 48 #define SCU0_RESET_PORTB_PHY3 36 49 #define SCU0_RESET_PORTB_XHCI 37 50 #define SCU0_RESET_PORTA_VHUB_EHCI 38 51 #define SCU0_RESET_PORTB_VHUB_EHCI 39 52 #define SCU0_RESET_UHCI 40 53 #define SCU0_RESET_TSP 41 54 #define SCU0_RESET_E2M0 42 55 #define SCU0_RESET_E2M1 43 56 #define SCU0_RESET_VLINK 44 57 58 /* SOC1 */ 59 #define SCU1_RESET_LPC0 0 60 #define SCU1_RESET_LPC1 1 61 #define SCU1_RESET_MII 2 62 #define SCU1_RESET_PECI 3 63 #define SCU1_RESET_PWM 4 64 #define SCU1_RESET_MAC0 5 65 #define SCU1_RESET_MAC1 6 66 #define SCU1_RESET_MAC2 7 67 #define SCU1_RESET_ADC 8 68 #define SCU1_RESET_SD 9 69 #define SCU1_RESET_ESPI0 10 70 #define SCU1_RESET_ESPI1 11 71 #define SCU1_RESET_JTAG1 12 72 #define SCU1_RESET_SPI0 13 73 #define SCU1_RESET_SPI1 14 74 #define SCU1_RESET_SPI2 15 75 #define SCU1_RESET_I3C0 16 76 #define SCU1_RESET_I3C1 17 77 #define SCU1_RESET_I3C2 18 78 #define SCU1_RESET_I3C3 19 79 #define SCU1_RESET_I3C4 20 80 #define SCU1_RESET_I3C5 21 81 #define SCU1_RESET_I3C6 22 82 #define SCU1_RESET_I3C7 23 83 #define SCU1_RESET_I3C8 24 84 #define SCU1_RESET_I3C9 25 85 #define SCU1_RESET_I3C10 26 86 #define SCU1_RESET_I3C11 27 87 #define SCU1_RESET_I3C12 28 88 #define SCU1_RESET_I3C13 29 89 #define SCU1_RESET_I3C14 30 90 #define SCU1_RESET_I3C15 31 91 #define SCU1_RESET_MCU0 32 92 #define SCU1_RESET_MCU1 33 93 #define SCU1_RESET_H2A_SPI1 34 94 #define SCU1_RESET_H2A_SPI2 35 95 #define SCU1_RESET_UART0 36 96 #define SCU1_RESET_UART1 37 97 #define SCU1_RESET_UART2 38 98 #define SCU1_RESET_UART3 39 99 #define SCU1_RESET_I2C_FILTER 40 100 #define SCU1_RESET_CALIPTRA 41 101 #define SCU1_RESET_XDMA 42 102 #define SCU1_RESET_FSI 43 103 #define SCU1_RESET_CAN 44 104 #define SCU1_RESET_MCTP 45 105 #define SCU1_RESET_I2C 46 106 #define SCU1_RESET_UART6 47 107 #define SCU1_RESET_UART7 48 108 #define SCU1_RESET_UART8 49 109 #define SCU1_RESET_UART9 50 110 #define SCU1_RESET_LTPI0 51 111 #define SCU1_RESET_VGAL 52 112 #define SCU1_RESET_LTPI1 53 113 #define SCU1_RESET_ACE 54 114 #define SCU1_RESET_E2M 55 115 #define SCU1_RESET_UHCI 56 116 #define SCU1_RESET_PORTC_USB2UART 57 117 #define SCU1_RESET_PORTC_VHUB_EHCI 58 118 #define SCU1_RESET_PORTD_USB2UART 59 119 #define SCU1_RESET_PORTD_VHUB_EHCI 60 120 #define SCU1_RESET_H2X 61 121 #define SCU1_RESET_I3CDMA 62 122 #define SCU1_RESET_PCIE2RST 63 123 124 #endif /* _MACH_ASPEED_AST2700_RESET_H_ */ 125