1*5d9730b9SXingyu Chen /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*5d9730b9SXingyu Chen * 3*5d9730b9SXingyu Chen * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4*5d9730b9SXingyu Chen * Author: Xingyu Chen <xingyu.chen@amlogic.com> 5*5d9730b9SXingyu Chen * 6*5d9730b9SXingyu Chen */ 7*5d9730b9SXingyu Chen 8*5d9730b9SXingyu Chen #ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 9*5d9730b9SXingyu Chen #define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 10*5d9730b9SXingyu Chen 11*5d9730b9SXingyu Chen /* RESET0 */ 12*5d9730b9SXingyu Chen /* 0 */ 13*5d9730b9SXingyu Chen #define RESET_AM2AXI_VAD 1 14*5d9730b9SXingyu Chen /* 2-3 */ 15*5d9730b9SXingyu Chen #define RESET_PSRAM 4 16*5d9730b9SXingyu Chen #define RESET_PAD_CTRL 5 17*5d9730b9SXingyu Chen /* 6 */ 18*5d9730b9SXingyu Chen #define RESET_TEMP_SENSOR 7 19*5d9730b9SXingyu Chen #define RESET_AM2AXI_DEV 8 20*5d9730b9SXingyu Chen /* 9 */ 21*5d9730b9SXingyu Chen #define RESET_SPICC_A 10 22*5d9730b9SXingyu Chen #define RESET_MSR_CLK 11 23*5d9730b9SXingyu Chen #define RESET_AUDIO 12 24*5d9730b9SXingyu Chen #define RESET_ANALOG_CTRL 13 25*5d9730b9SXingyu Chen #define RESET_SAR_ADC 14 26*5d9730b9SXingyu Chen #define RESET_AUDIO_VAD 15 27*5d9730b9SXingyu Chen #define RESET_CEC 16 28*5d9730b9SXingyu Chen #define RESET_PWM_EF 17 29*5d9730b9SXingyu Chen #define RESET_PWM_CD 18 30*5d9730b9SXingyu Chen #define RESET_PWM_AB 19 31*5d9730b9SXingyu Chen /* 20 */ 32*5d9730b9SXingyu Chen #define RESET_IR_CTRL 21 33*5d9730b9SXingyu Chen #define RESET_I2C_S_A 22 34*5d9730b9SXingyu Chen /* 23 */ 35*5d9730b9SXingyu Chen #define RESET_I2C_M_D 24 36*5d9730b9SXingyu Chen #define RESET_I2C_M_C 25 37*5d9730b9SXingyu Chen #define RESET_I2C_M_B 26 38*5d9730b9SXingyu Chen #define RESET_I2C_M_A 27 39*5d9730b9SXingyu Chen #define RESET_I2C_PROD_AHB 28 40*5d9730b9SXingyu Chen #define RESET_I2C_PROD 29 41*5d9730b9SXingyu Chen /* 30-31 */ 42*5d9730b9SXingyu Chen 43*5d9730b9SXingyu Chen /* RESET1 */ 44*5d9730b9SXingyu Chen #define RESET_ACODEC 32 45*5d9730b9SXingyu Chen #define RESET_DMA 33 46*5d9730b9SXingyu Chen #define RESET_SD_EMMC_A 34 47*5d9730b9SXingyu Chen /* 35 */ 48*5d9730b9SXingyu Chen #define RESET_USBCTRL 36 49*5d9730b9SXingyu Chen /* 37 */ 50*5d9730b9SXingyu Chen #define RESET_USBPHY 38 51*5d9730b9SXingyu Chen /* 39-41 */ 52*5d9730b9SXingyu Chen #define RESET_RSA 42 53*5d9730b9SXingyu Chen #define RESET_DMC 43 54*5d9730b9SXingyu Chen /* 44 */ 55*5d9730b9SXingyu Chen #define RESET_IRQ_CTRL 45 56*5d9730b9SXingyu Chen /* 46 */ 57*5d9730b9SXingyu Chen #define RESET_NIC_VAD 47 58*5d9730b9SXingyu Chen #define RESET_NIC_AXI 48 59*5d9730b9SXingyu Chen #define RESET_RAMA 49 60*5d9730b9SXingyu Chen #define RESET_RAMB 50 61*5d9730b9SXingyu Chen /* 51-52 */ 62*5d9730b9SXingyu Chen #define RESET_ROM 53 63*5d9730b9SXingyu Chen #define RESET_SPIFC 54 64*5d9730b9SXingyu Chen #define RESET_GIC 55 65*5d9730b9SXingyu Chen #define RESET_UART_C 56 66*5d9730b9SXingyu Chen #define RESET_UART_B 57 67*5d9730b9SXingyu Chen #define RESET_UART_A 58 68*5d9730b9SXingyu Chen #define RESET_OSC_RING 59 69*5d9730b9SXingyu Chen /* 60-63 */ 70*5d9730b9SXingyu Chen 71*5d9730b9SXingyu Chen /* RESET2 */ 72*5d9730b9SXingyu Chen /* 64-95 */ 73*5d9730b9SXingyu Chen 74*5d9730b9SXingyu Chen #endif 75