1b16a0063SNeil Armstrong /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 279795e20SNeil Armstrong /* 379795e20SNeil Armstrong * Copyright (c) 2016 BayLibre, SAS. 479795e20SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 579795e20SNeil Armstrong */ 679795e20SNeil Armstrong #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H 779795e20SNeil Armstrong #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H 879795e20SNeil Armstrong 979795e20SNeil Armstrong /* RESET0 */ 1079795e20SNeil Armstrong #define RESET_HIU 0 1179795e20SNeil Armstrong /* 1 */ 1279795e20SNeil Armstrong #define RESET_DOS_RESET 2 1379795e20SNeil Armstrong #define RESET_DDR_TOP 3 1479795e20SNeil Armstrong #define RESET_DCU_RESET 4 1579795e20SNeil Armstrong #define RESET_VIU 5 1679795e20SNeil Armstrong #define RESET_AIU 6 1779795e20SNeil Armstrong #define RESET_VID_PLL_DIV 7 1879795e20SNeil Armstrong /* 8 */ 1979795e20SNeil Armstrong #define RESET_PMUX 9 2079795e20SNeil Armstrong #define RESET_VENC 10 2179795e20SNeil Armstrong #define RESET_ASSIST 11 2279795e20SNeil Armstrong #define RESET_AFIFO2 12 2379795e20SNeil Armstrong #define RESET_VCBUS 13 2479795e20SNeil Armstrong /* 14 */ 2579795e20SNeil Armstrong /* 15 */ 2679795e20SNeil Armstrong #define RESET_GIC 16 2779795e20SNeil Armstrong #define RESET_CAPB3_DECODE 17 2879795e20SNeil Armstrong #define RESET_NAND_CAPB3 18 2979795e20SNeil Armstrong #define RESET_HDMITX_CAPB3 19 3079795e20SNeil Armstrong #define RESET_MALI_CAPB3 20 3179795e20SNeil Armstrong #define RESET_DOS_CAPB3 21 3279795e20SNeil Armstrong #define RESET_SYS_CPU_CAPB3 22 3379795e20SNeil Armstrong #define RESET_CBUS_CAPB3 23 3479795e20SNeil Armstrong #define RESET_AHB_CNTL 24 3579795e20SNeil Armstrong #define RESET_AHB_DATA 25 3679795e20SNeil Armstrong #define RESET_VCBUS_CLK81 26 3779795e20SNeil Armstrong #define RESET_MMC 27 3879795e20SNeil Armstrong #define RESET_MIPI_0 28 3979795e20SNeil Armstrong #define RESET_MIPI_1 29 4079795e20SNeil Armstrong #define RESET_MIPI_2 30 4179795e20SNeil Armstrong #define RESET_MIPI_3 31 4279795e20SNeil Armstrong /* RESET1 */ 4379795e20SNeil Armstrong #define RESET_CPPM 32 4479795e20SNeil Armstrong #define RESET_DEMUX 33 4579795e20SNeil Armstrong #define RESET_USB_OTG 34 4679795e20SNeil Armstrong #define RESET_DDR 35 4779795e20SNeil Armstrong #define RESET_AO_RESET 36 4879795e20SNeil Armstrong #define RESET_BT656 37 4979795e20SNeil Armstrong #define RESET_AHB_SRAM 38 5079795e20SNeil Armstrong /* 39 */ 5179795e20SNeil Armstrong #define RESET_PARSER 40 5279795e20SNeil Armstrong #define RESET_BLKMV 41 5379795e20SNeil Armstrong #define RESET_ISA 42 5479795e20SNeil Armstrong #define RESET_ETHERNET 43 5579795e20SNeil Armstrong #define RESET_SD_EMMC_A 44 5679795e20SNeil Armstrong #define RESET_SD_EMMC_B 45 5779795e20SNeil Armstrong #define RESET_SD_EMMC_C 46 5879795e20SNeil Armstrong #define RESET_ROM_BOOT 47 5979795e20SNeil Armstrong #define RESET_SYS_CPU_0 48 6079795e20SNeil Armstrong #define RESET_SYS_CPU_1 49 6179795e20SNeil Armstrong #define RESET_SYS_CPU_2 50 6279795e20SNeil Armstrong #define RESET_SYS_CPU_3 51 6379795e20SNeil Armstrong #define RESET_SYS_CPU_CORE_0 52 6479795e20SNeil Armstrong #define RESET_SYS_CPU_CORE_1 53 6579795e20SNeil Armstrong #define RESET_SYS_CPU_CORE_2 54 6679795e20SNeil Armstrong #define RESET_SYS_CPU_CORE_3 55 6779795e20SNeil Armstrong #define RESET_SYS_PLL_DIV 56 6879795e20SNeil Armstrong #define RESET_SYS_CPU_AXI 57 6979795e20SNeil Armstrong #define RESET_SYS_CPU_L2 58 7079795e20SNeil Armstrong #define RESET_SYS_CPU_P 59 7179795e20SNeil Armstrong #define RESET_SYS_CPU_MBIST 60 72*3a5fc252SJerome Brunet #define RESET_ACODEC 61 7379795e20SNeil Armstrong /* 62 */ 7479795e20SNeil Armstrong /* 63 */ 7579795e20SNeil Armstrong /* RESET2 */ 7679795e20SNeil Armstrong #define RESET_VD_RMEM 64 7779795e20SNeil Armstrong #define RESET_AUDIN 65 7879795e20SNeil Armstrong #define RESET_HDMI_TX 66 7979795e20SNeil Armstrong /* 67 */ 8079795e20SNeil Armstrong /* 68 */ 8179795e20SNeil Armstrong /* 69 */ 8279795e20SNeil Armstrong #define RESET_GE2D 70 8379795e20SNeil Armstrong #define RESET_PARSER_REG 71 8479795e20SNeil Armstrong #define RESET_PARSER_FETCH 72 8579795e20SNeil Armstrong #define RESET_PARSER_CTL 73 8679795e20SNeil Armstrong #define RESET_PARSER_TOP 74 8779795e20SNeil Armstrong /* 75 */ 8879795e20SNeil Armstrong /* 76 */ 8979795e20SNeil Armstrong #define RESET_AO_CPU_RESET 77 9079795e20SNeil Armstrong #define RESET_MALI 78 9179795e20SNeil Armstrong #define RESET_HDMI_SYSTEM_RESET 79 9279795e20SNeil Armstrong /* 80-95 */ 9379795e20SNeil Armstrong /* RESET3 */ 9479795e20SNeil Armstrong #define RESET_RING_OSCILLATOR 96 9579795e20SNeil Armstrong #define RESET_SYS_CPU 97 9679795e20SNeil Armstrong #define RESET_EFUSE 98 9779795e20SNeil Armstrong #define RESET_SYS_CPU_BVCI 99 9879795e20SNeil Armstrong #define RESET_AIFIFO 100 9979795e20SNeil Armstrong #define RESET_TVFE 101 10079795e20SNeil Armstrong #define RESET_AHB_BRIDGE_CNTL 102 10179795e20SNeil Armstrong /* 103 */ 10279795e20SNeil Armstrong #define RESET_AUDIO_DAC 104 10379795e20SNeil Armstrong #define RESET_DEMUX_TOP 105 10479795e20SNeil Armstrong #define RESET_DEMUX_DES 106 10579795e20SNeil Armstrong #define RESET_DEMUX_S2P_0 107 10679795e20SNeil Armstrong #define RESET_DEMUX_S2P_1 108 10779795e20SNeil Armstrong #define RESET_DEMUX_RESET_0 109 10879795e20SNeil Armstrong #define RESET_DEMUX_RESET_1 110 10979795e20SNeil Armstrong #define RESET_DEMUX_RESET_2 111 11079795e20SNeil Armstrong /* 112-127 */ 11179795e20SNeil Armstrong /* RESET4 */ 11279795e20SNeil Armstrong /* 128 */ 11379795e20SNeil Armstrong /* 129 */ 11479795e20SNeil Armstrong /* 130 */ 11579795e20SNeil Armstrong /* 131 */ 11679795e20SNeil Armstrong #define RESET_DVIN_RESET 132 11779795e20SNeil Armstrong #define RESET_RDMA 133 11879795e20SNeil Armstrong #define RESET_VENCI 134 11979795e20SNeil Armstrong #define RESET_VENCP 135 12079795e20SNeil Armstrong /* 136 */ 12179795e20SNeil Armstrong #define RESET_VDAC 137 12279795e20SNeil Armstrong #define RESET_RTC 138 12379795e20SNeil Armstrong /* 139 */ 12479795e20SNeil Armstrong #define RESET_VDI6 140 12579795e20SNeil Armstrong #define RESET_VENCL 141 12679795e20SNeil Armstrong #define RESET_I2C_MASTER_2 142 12779795e20SNeil Armstrong #define RESET_I2C_MASTER_1 143 12879795e20SNeil Armstrong /* 144-159 */ 12979795e20SNeil Armstrong /* RESET5 */ 13079795e20SNeil Armstrong /* 160-191 */ 13179795e20SNeil Armstrong /* RESET6 */ 13279795e20SNeil Armstrong #define RESET_PERIPHS_GENERAL 192 13379795e20SNeil Armstrong #define RESET_PERIPHS_SPICC 193 13479795e20SNeil Armstrong #define RESET_PERIPHS_SMART_CARD 194 13579795e20SNeil Armstrong #define RESET_PERIPHS_SAR_ADC 195 13679795e20SNeil Armstrong #define RESET_PERIPHS_I2C_MASTER_0 196 13779795e20SNeil Armstrong #define RESET_SANA 197 13879795e20SNeil Armstrong /* 198 */ 13979795e20SNeil Armstrong #define RESET_PERIPHS_STREAM_INTERFACE 199 14079795e20SNeil Armstrong #define RESET_PERIPHS_SDIO 200 14179795e20SNeil Armstrong #define RESET_PERIPHS_UART_0 201 14279795e20SNeil Armstrong #define RESET_PERIPHS_UART_1_2 202 14379795e20SNeil Armstrong #define RESET_PERIPHS_ASYNC_0 203 14479795e20SNeil Armstrong #define RESET_PERIPHS_ASYNC_1 204 14579795e20SNeil Armstrong #define RESET_PERIPHS_SPI_0 205 14679795e20SNeil Armstrong #define RESET_PERIPHS_SDHC 206 14779795e20SNeil Armstrong #define RESET_UART_SLIP 207 14879795e20SNeil Armstrong /* 208-223 */ 14979795e20SNeil Armstrong /* RESET7 */ 15079795e20SNeil Armstrong #define RESET_USB_DDR_0 224 15179795e20SNeil Armstrong #define RESET_USB_DDR_1 225 15279795e20SNeil Armstrong #define RESET_USB_DDR_2 226 15379795e20SNeil Armstrong #define RESET_USB_DDR_3 227 15479795e20SNeil Armstrong /* 228 */ 15579795e20SNeil Armstrong #define RESET_DEVICE_MMC_ARB 229 15679795e20SNeil Armstrong /* 230 */ 15779795e20SNeil Armstrong #define RESET_VID_LOCK 231 15879795e20SNeil Armstrong #define RESET_A9_DMC_PIPEL 232 15979795e20SNeil Armstrong /* 233-255 */ 16079795e20SNeil Armstrong 16179795e20SNeil Armstrong #endif 162