xref: /linux/include/dt-bindings/reset/altr,rst-mgr-s10.h (revision 981368e1440b76f68b1ac8f5fb14e739f80ecc4e)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2016 Intel Corporation. All rights reserved
4  * Copyright (C) 2016 Altera Corporation. All rights reserved
5  *
6  * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
7  */
8 
9 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
10 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
11 
12 /* MPUMODRST */
13 #define CPU0_RESET		0
14 #define CPU1_RESET		1
15 #define CPU2_RESET		2
16 #define CPU3_RESET		3
17 
18 /* PER0MODRST */
19 #define EMAC0_RESET		32
20 #define EMAC1_RESET		33
21 #define EMAC2_RESET		34
22 #define USB0_RESET		35
23 #define USB1_RESET		36
24 #define NAND_RESET		37
25 /* 38 is empty */
26 #define SDMMC_RESET		39
27 #define EMAC0_OCP_RESET		40
28 #define EMAC1_OCP_RESET		41
29 #define EMAC2_OCP_RESET		42
30 #define USB0_OCP_RESET		43
31 #define USB1_OCP_RESET		44
32 #define NAND_OCP_RESET		45
33 /* 46 is empty */
34 #define SDMMC_OCP_RESET		47
35 #define DMA_RESET		48
36 #define SPIM0_RESET		49
37 #define SPIM1_RESET		50
38 #define SPIS0_RESET		51
39 #define SPIS1_RESET		52
40 #define DMA_OCP_RESET		53
41 #define EMAC_PTP_RESET		54
42 /* 55 is empty*/
43 #define DMAIF0_RESET		56
44 #define DMAIF1_RESET		57
45 #define DMAIF2_RESET		58
46 #define DMAIF3_RESET		59
47 #define DMAIF4_RESET		60
48 #define DMAIF5_RESET		61
49 #define DMAIF6_RESET		62
50 #define DMAIF7_RESET		63
51 
52 /* PER1MODRST */
53 #define WATCHDOG0_RESET		64
54 #define WATCHDOG1_RESET		65
55 #define WATCHDOG2_RESET		66
56 #define WATCHDOG3_RESET		67
57 #define L4SYSTIMER0_RESET	68
58 #define L4SYSTIMER1_RESET	69
59 #define SPTIMER0_RESET		70
60 #define SPTIMER1_RESET		71
61 #define I2C0_RESET		72
62 #define I2C1_RESET		73
63 #define I2C2_RESET		74
64 #define I2C3_RESET		75
65 #define I2C4_RESET		76
66 #define I3C0_RESET		77
67 #define I3C1_RESET		78
68 /* 79 is empty */
69 #define UART0_RESET		80
70 #define UART1_RESET		81
71 /* 82-87 is empty */
72 #define GPIO0_RESET		88
73 #define GPIO1_RESET		89
74 #define WATCHDOG4_RESET		90
75 
76 /* BRGMODRST */
77 #define SOC2FPGA_RESET		96
78 #define LWHPS2FPGA_RESET	97
79 #define FPGA2SOC_RESET		98
80 #define F2SSDRAM0_RESET		99
81 #define F2SSDRAM1_RESET		100
82 #define F2SSDRAM2_RESET		101
83 #define DDRSCH_RESET		102
84 
85 /* COLDMODRST */
86 #define CPUPO0_RESET		160
87 #define CPUPO1_RESET		161
88 #define CPUPO2_RESET		162
89 #define CPUPO3_RESET		163
90 /* 164-167 is empty */
91 #define L2_RESET		168
92 
93 /* DBGMODRST */
94 #define DBG_RESET		224
95 #define CSDAP_RESET		225
96 
97 /* TAPMODRST */
98 #define TAP_RESET		256
99 
100 #endif
101