1*94764350SMikhail Kshevetskiy /* SPDX-License-Identifier: GPL-2.0-only */ 2*94764350SMikhail Kshevetskiy /* 3*94764350SMikhail Kshevetskiy * Copyright (C) 2024 iopsys Software Solutions AB. 4*94764350SMikhail Kshevetskiy * Copyright (C) 2025 Genexis AB. 5*94764350SMikhail Kshevetskiy * 6*94764350SMikhail Kshevetskiy * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> 7*94764350SMikhail Kshevetskiy * 8*94764350SMikhail Kshevetskiy * based on 9*94764350SMikhail Kshevetskiy * include/dt-bindings/reset/airoha,en7581-reset.h 10*94764350SMikhail Kshevetskiy * by Lorenzo Bianconi <lorenzo@kernel.org> 11*94764350SMikhail Kshevetskiy */ 12*94764350SMikhail Kshevetskiy 13*94764350SMikhail Kshevetskiy #ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ 14*94764350SMikhail Kshevetskiy #define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ 15*94764350SMikhail Kshevetskiy 16*94764350SMikhail Kshevetskiy /* RST_CTRL2 */ 17*94764350SMikhail Kshevetskiy #define EN7523_XPON_PHY_RST 0 18*94764350SMikhail Kshevetskiy #define EN7523_XSI_MAC_RST 1 19*94764350SMikhail Kshevetskiy #define EN7523_XSI_PHY_RST 2 20*94764350SMikhail Kshevetskiy #define EN7523_NPU_RST 3 21*94764350SMikhail Kshevetskiy #define EN7523_I2S_RST 4 22*94764350SMikhail Kshevetskiy #define EN7523_TRNG_RST 5 23*94764350SMikhail Kshevetskiy #define EN7523_TRNG_MSTART_RST 6 24*94764350SMikhail Kshevetskiy #define EN7523_DUAL_HSI0_RST 7 25*94764350SMikhail Kshevetskiy #define EN7523_DUAL_HSI1_RST 8 26*94764350SMikhail Kshevetskiy #define EN7523_HSI_RST 9 27*94764350SMikhail Kshevetskiy #define EN7523_DUAL_HSI0_MAC_RST 10 28*94764350SMikhail Kshevetskiy #define EN7523_DUAL_HSI1_MAC_RST 11 29*94764350SMikhail Kshevetskiy #define EN7523_HSI_MAC_RST 12 30*94764350SMikhail Kshevetskiy #define EN7523_WDMA_RST 13 31*94764350SMikhail Kshevetskiy #define EN7523_WOE0_RST 14 32*94764350SMikhail Kshevetskiy #define EN7523_WOE1_RST 15 33*94764350SMikhail Kshevetskiy #define EN7523_HSDMA_RST 16 34*94764350SMikhail Kshevetskiy #define EN7523_I2C2RBUS_RST 17 35*94764350SMikhail Kshevetskiy #define EN7523_TDMA_RST 18 36*94764350SMikhail Kshevetskiy /* RST_CTRL1 */ 37*94764350SMikhail Kshevetskiy #define EN7523_PCM1_ZSI_ISI_RST 19 38*94764350SMikhail Kshevetskiy #define EN7523_FE_PDMA_RST 20 39*94764350SMikhail Kshevetskiy #define EN7523_FE_QDMA_RST 21 40*94764350SMikhail Kshevetskiy #define EN7523_PCM_SPIWP_RST 22 41*94764350SMikhail Kshevetskiy #define EN7523_CRYPTO_RST 23 42*94764350SMikhail Kshevetskiy #define EN7523_TIMER_RST 24 43*94764350SMikhail Kshevetskiy #define EN7523_PCM1_RST 25 44*94764350SMikhail Kshevetskiy #define EN7523_UART_RST 26 45*94764350SMikhail Kshevetskiy #define EN7523_GPIO_RST 27 46*94764350SMikhail Kshevetskiy #define EN7523_GDMA_RST 28 47*94764350SMikhail Kshevetskiy #define EN7523_I2C_MASTER_RST 29 48*94764350SMikhail Kshevetskiy #define EN7523_PCM2_ZSI_ISI_RST 30 49*94764350SMikhail Kshevetskiy #define EN7523_SFC_RST 31 50*94764350SMikhail Kshevetskiy #define EN7523_UART2_RST 32 51*94764350SMikhail Kshevetskiy #define EN7523_GDMP_RST 33 52*94764350SMikhail Kshevetskiy #define EN7523_FE_RST 34 53*94764350SMikhail Kshevetskiy #define EN7523_USB_HOST_P0_RST 35 54*94764350SMikhail Kshevetskiy #define EN7523_GSW_RST 36 55*94764350SMikhail Kshevetskiy #define EN7523_SFC2_PCM_RST 37 56*94764350SMikhail Kshevetskiy #define EN7523_PCIE0_RST 38 57*94764350SMikhail Kshevetskiy #define EN7523_PCIE1_RST 39 58*94764350SMikhail Kshevetskiy #define EN7523_PCIE_HB_RST 40 59*94764350SMikhail Kshevetskiy #define EN7523_XPON_MAC_RST 41 60*94764350SMikhail Kshevetskiy 61*94764350SMikhail Kshevetskiy #endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ */ 62