xref: /linux/include/dt-bindings/reset/actions,s500-reset.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1*fac1d443SCristian Ciocaltea /* SPDX-License-Identifier: GPL-2.0+ */
2*fac1d443SCristian Ciocaltea /*
3*fac1d443SCristian Ciocaltea  * Device Tree binding constants for Actions Semi S500 Reset Management Unit
4*fac1d443SCristian Ciocaltea  *
5*fac1d443SCristian Ciocaltea  * Copyright (c) 2014 Actions Semi Inc.
6*fac1d443SCristian Ciocaltea  * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
7*fac1d443SCristian Ciocaltea  */
8*fac1d443SCristian Ciocaltea 
9*fac1d443SCristian Ciocaltea #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
10*fac1d443SCristian Ciocaltea #define __DT_BINDINGS_ACTIONS_S500_RESET_H
11*fac1d443SCristian Ciocaltea 
12*fac1d443SCristian Ciocaltea #define RESET_DMAC				0
13*fac1d443SCristian Ciocaltea #define RESET_NORIF				1
14*fac1d443SCristian Ciocaltea #define RESET_DDR				2
15*fac1d443SCristian Ciocaltea #define RESET_NANDC				3
16*fac1d443SCristian Ciocaltea #define RESET_SD0				4
17*fac1d443SCristian Ciocaltea #define RESET_SD1				5
18*fac1d443SCristian Ciocaltea #define RESET_PCM1				6
19*fac1d443SCristian Ciocaltea #define RESET_DE				7
20*fac1d443SCristian Ciocaltea #define RESET_LCD				8
21*fac1d443SCristian Ciocaltea #define RESET_SD2				9
22*fac1d443SCristian Ciocaltea #define RESET_DSI				10
23*fac1d443SCristian Ciocaltea #define RESET_CSI				11
24*fac1d443SCristian Ciocaltea #define RESET_BISP				12
25*fac1d443SCristian Ciocaltea #define RESET_KEY				13
26*fac1d443SCristian Ciocaltea #define RESET_GPIO				14
27*fac1d443SCristian Ciocaltea #define RESET_AUDIO				15
28*fac1d443SCristian Ciocaltea #define RESET_PCM0				16
29*fac1d443SCristian Ciocaltea #define RESET_VDE				17
30*fac1d443SCristian Ciocaltea #define RESET_VCE				18
31*fac1d443SCristian Ciocaltea #define RESET_GPU3D				19
32*fac1d443SCristian Ciocaltea #define RESET_NIC301				20
33*fac1d443SCristian Ciocaltea #define RESET_LENS				21
34*fac1d443SCristian Ciocaltea #define RESET_PERIPHRESET			22
35*fac1d443SCristian Ciocaltea #define RESET_USB2_0				23
36*fac1d443SCristian Ciocaltea #define RESET_TVOUT				24
37*fac1d443SCristian Ciocaltea #define RESET_HDMI				25
38*fac1d443SCristian Ciocaltea #define RESET_HDCP2TX				26
39*fac1d443SCristian Ciocaltea #define RESET_UART6				27
40*fac1d443SCristian Ciocaltea #define RESET_UART0				28
41*fac1d443SCristian Ciocaltea #define RESET_UART1				29
42*fac1d443SCristian Ciocaltea #define RESET_UART2				30
43*fac1d443SCristian Ciocaltea #define RESET_SPI0				31
44*fac1d443SCristian Ciocaltea #define RESET_SPI1				32
45*fac1d443SCristian Ciocaltea #define RESET_SPI2				33
46*fac1d443SCristian Ciocaltea #define RESET_SPI3				34
47*fac1d443SCristian Ciocaltea #define RESET_I2C0				35
48*fac1d443SCristian Ciocaltea #define RESET_I2C1				36
49*fac1d443SCristian Ciocaltea #define RESET_USB3				37
50*fac1d443SCristian Ciocaltea #define RESET_UART3				38
51*fac1d443SCristian Ciocaltea #define RESET_UART4				39
52*fac1d443SCristian Ciocaltea #define RESET_UART5				40
53*fac1d443SCristian Ciocaltea #define RESET_I2C2				41
54*fac1d443SCristian Ciocaltea #define RESET_I2C3				42
55*fac1d443SCristian Ciocaltea #define RESET_ETHERNET				43
56*fac1d443SCristian Ciocaltea #define RESET_CHIPID				44
57*fac1d443SCristian Ciocaltea #define RESET_USB2_1				45
58*fac1d443SCristian Ciocaltea #define RESET_WD0RESET				46
59*fac1d443SCristian Ciocaltea #define RESET_WD1RESET				47
60*fac1d443SCristian Ciocaltea #define RESET_WD2RESET				48
61*fac1d443SCristian Ciocaltea #define RESET_WD3RESET				49
62*fac1d443SCristian Ciocaltea #define RESET_DBG0RESET				50
63*fac1d443SCristian Ciocaltea #define RESET_DBG1RESET				51
64*fac1d443SCristian Ciocaltea #define RESET_DBG2RESET				52
65*fac1d443SCristian Ciocaltea #define RESET_DBG3RESET				53
66*fac1d443SCristian Ciocaltea 
67*fac1d443SCristian Ciocaltea #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
68