1*58f7381cSLad Prabhakar /* SPDX-License-Identifier: GPL-2.0 2*58f7381cSLad Prabhakar * 3*58f7381cSLad Prabhakar * Copyright (C) 2020 Renesas Electronics Corp. 4*58f7381cSLad Prabhakar */ 5*58f7381cSLad Prabhakar #ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__ 6*58f7381cSLad Prabhakar #define __DT_BINDINGS_POWER_R8A7742_SYSC_H__ 7*58f7381cSLad Prabhakar 8*58f7381cSLad Prabhakar /* 9*58f7381cSLad Prabhakar * These power domain indices match the numbers of the interrupt bits 10*58f7381cSLad Prabhakar * representing the power areas in the various Interrupt Registers 11*58f7381cSLad Prabhakar * (e.g. SYSCISR, Interrupt Status Register) 12*58f7381cSLad Prabhakar */ 13*58f7381cSLad Prabhakar 14*58f7381cSLad Prabhakar #define R8A7742_PD_CA15_CPU0 0 15*58f7381cSLad Prabhakar #define R8A7742_PD_CA15_CPU1 1 16*58f7381cSLad Prabhakar #define R8A7742_PD_CA15_CPU2 2 17*58f7381cSLad Prabhakar #define R8A7742_PD_CA15_CPU3 3 18*58f7381cSLad Prabhakar #define R8A7742_PD_CA7_CPU0 5 19*58f7381cSLad Prabhakar #define R8A7742_PD_CA7_CPU1 6 20*58f7381cSLad Prabhakar #define R8A7742_PD_CA7_CPU2 7 21*58f7381cSLad Prabhakar #define R8A7742_PD_CA7_CPU3 8 22*58f7381cSLad Prabhakar #define R8A7742_PD_CA15_SCU 12 23*58f7381cSLad Prabhakar #define R8A7742_PD_RGX 20 24*58f7381cSLad Prabhakar #define R8A7742_PD_CA7_SCU 21 25*58f7381cSLad Prabhakar 26*58f7381cSLad Prabhakar /* Always-on power area */ 27*58f7381cSLad Prabhakar #define R8A7742_PD_ALWAYS_ON 32 28*58f7381cSLad Prabhakar 29*58f7381cSLad Prabhakar #endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */ 30