1*86a378bbSEnric Balletbo i Serra /* SPDX-License-Identifier: GPL-2.0 */ 2*86a378bbSEnric Balletbo i Serra /* 3*86a378bbSEnric Balletbo i Serra * Copyright (c) 2020 MediaTek Inc. 4*86a378bbSEnric Balletbo i Serra * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5*86a378bbSEnric Balletbo i Serra */ 6*86a378bbSEnric Balletbo i Serra 7*86a378bbSEnric Balletbo i Serra #ifndef _DT_BINDINGS_POWER_MT8183_POWER_H 8*86a378bbSEnric Balletbo i Serra #define _DT_BINDINGS_POWER_MT8183_POWER_H 9*86a378bbSEnric Balletbo i Serra 10*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_AUDIO 0 11*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_CONN 1 12*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_MFG_ASYNC 2 13*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_MFG 3 14*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_MFG_CORE0 4 15*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_MFG_CORE1 5 16*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_MFG_2D 6 17*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_DISP 7 18*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_CAM 8 19*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_ISP 9 20*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_VDEC 10 21*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_VENC 11 22*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_VPU_TOP 12 23*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_VPU_CORE0 13 24*86a378bbSEnric Balletbo i Serra #define MT8183_POWER_DOMAIN_VPU_CORE1 14 25*86a378bbSEnric Balletbo i Serra 26*86a378bbSEnric Balletbo i Serra #endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ 27