xref: /linux/include/dt-bindings/power/amlogic,a9-pwrc.h (revision 67f8bc848ee31831336bd478e57d2f993551902e)
1*2d055fb2SXianwei Zhao /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2*2d055fb2SXianwei Zhao /*
3*2d055fb2SXianwei Zhao  * Copyright (C) 2026 Amlogic, Inc. All rights reserved
4*2d055fb2SXianwei Zhao  */
5*2d055fb2SXianwei Zhao 
6*2d055fb2SXianwei Zhao #ifndef _DT_BINDINGS_AMLOGIC_A9_POWER_H
7*2d055fb2SXianwei Zhao #define _DT_BINDINGS_AMLOGIC_A9_POWER_H
8*2d055fb2SXianwei Zhao 
9*2d055fb2SXianwei Zhao #define PWRC_A9_DSPA_ID			0
10*2d055fb2SXianwei Zhao #define PWRC_A9_U3HSG_U3_ID		1
11*2d055fb2SXianwei Zhao #define PWRC_A9_DP_ID			2
12*2d055fb2SXianwei Zhao #define PWRC_A9_DOS_HCODEC_ID		3
13*2d055fb2SXianwei Zhao #define PWRC_A9_TAHOE_ID		4
14*2d055fb2SXianwei Zhao #define PWRC_A9_DOS_HEVC_ID		5
15*2d055fb2SXianwei Zhao #define PWRC_A9_U2H_ID			6
16*2d055fb2SXianwei Zhao #define PWRC_A9_U3DRD_B_ID		7
17*2d055fb2SXianwei Zhao #define PWRC_A9_VPU_HDMI_ID		8
18*2d055fb2SXianwei Zhao #define PWRC_A9_U2DRD_ID		9
19*2d055fb2SXianwei Zhao #define PWRC_A9_U3DRD_A_ID		10
20*2d055fb2SXianwei Zhao #define PWRC_A9_SD_EMMC_C_ID		11
21*2d055fb2SXianwei Zhao #define PWRC_A9_GE2D_ID			12
22*2d055fb2SXianwei Zhao #define PWRC_A9_AMFC_ID			13
23*2d055fb2SXianwei Zhao #define PWRC_A9_EDPTX_ID		14
24*2d055fb2SXianwei Zhao #define PWRC_A9_OPP_ID			15
25*2d055fb2SXianwei Zhao #define PWRC_A9_VICP_ID			16
26*2d055fb2SXianwei Zhao #define PWRC_A9_SD_EMMC_A_ID		17
27*2d055fb2SXianwei Zhao #define PWRC_A9_SD_EMMC_B_ID		18
28*2d055fb2SXianwei Zhao #define PWRC_A9_ETH_ID			19
29*2d055fb2SXianwei Zhao #define PWRC_A9_PCIE_A_ID		20
30*2d055fb2SXianwei Zhao #define PWRC_A9_PCIE_B_ID		21
31*2d055fb2SXianwei Zhao #define PWRC_A9_NNA_4T_ID		22
32*2d055fb2SXianwei Zhao #define PWRC_A9_HDMIRX_ID		23
33*2d055fb2SXianwei Zhao #define PWRC_A9_CVE_ID			24
34*2d055fb2SXianwei Zhao #define PWRC_A9_ISP_ID			25
35*2d055fb2SXianwei Zhao #define PWRC_A9_ETH_1G_ID		26
36*2d055fb2SXianwei Zhao #define PWRC_A9_U3HSG_HSG_ID		27
37*2d055fb2SXianwei Zhao #define PWRC_A9_U3DPPHY_U3_ID		28
38*2d055fb2SXianwei Zhao #define PWRC_A9_U3DPPHY_DP_ID		29
39*2d055fb2SXianwei Zhao #define PWRC_A9_PCIE3PHY_ID		30
40*2d055fb2SXianwei Zhao #define PWRC_A9_U3HSG_PCIE2_ID		31
41*2d055fb2SXianwei Zhao #define PWRC_A9_MALI_TOP_ID		32
42*2d055fb2SXianwei Zhao #define PWRC_A9_AO_SED_ID		33
43*2d055fb2SXianwei Zhao #define PWRC_A9_AO_IR_ID		34
44*2d055fb2SXianwei Zhao #define PWRC_A9_AO_UART_B_ID		35
45*2d055fb2SXianwei Zhao #define PWRC_A9_AO_UART_C_ID		36
46*2d055fb2SXianwei Zhao #define PWRC_A9_AO_UART_D_ID		37
47*2d055fb2SXianwei Zhao #define PWRC_A9_AO_SPISG_ID		38
48*2d055fb2SXianwei Zhao #define PWRC_A9_AO_UART_E_ID		39
49*2d055fb2SXianwei Zhao #define PWRC_A9_AO_CEC_ID		40
50*2d055fb2SXianwei Zhao #define PWRC_A9_EE_SRAMA_ID		41
51*2d055fb2SXianwei Zhao #define PWRC_A9_AUDIO_ID		42
52*2d055fb2SXianwei Zhao #define PWRC_A9_DMC0_ID			43
53*2d055fb2SXianwei Zhao #define PWRC_A9_GIC_ID			44
54*2d055fb2SXianwei Zhao #define PWRC_A9_DDRPHY_ID		45
55*2d055fb2SXianwei Zhao #define PWRC_A9_AUCPU_ID		46
56*2d055fb2SXianwei Zhao #define PWRC_A9_DSI0_ID			47
57*2d055fb2SXianwei Zhao #define PWRC_A9_DSI1_ID			48
58*2d055fb2SXianwei Zhao #define PWRC_A9_CAN0_ID			49
59*2d055fb2SXianwei Zhao #define PWRC_A9_CAN1_ID			50
60*2d055fb2SXianwei Zhao 
61*2d055fb2SXianwei Zhao #endif
62