1c65176fdSRoger Quadros /* SPDX-License-Identifier: GPL-2.0 */ 2c65176fdSRoger Quadros /* 3c65176fdSRoger Quadros * This header provides constants for SERDES MUX for TI SoCs 4c65176fdSRoger Quadros */ 5c65176fdSRoger Quadros 6c65176fdSRoger Quadros #ifndef _DT_BINDINGS_MUX_TI_SERDES 7c65176fdSRoger Quadros #define _DT_BINDINGS_MUX_TI_SERDES 8c65176fdSRoger Quadros 9*5438d75fSJayesh Choudhary /* 10*5438d75fSJayesh Choudhary * These bindings are deprecated, because they do not match the actual 11*5438d75fSJayesh Choudhary * concept of bindings but rather contain pure constants values used only 12*5438d75fSJayesh Choudhary * in DTS board files. 13*5438d75fSJayesh Choudhary * Instead include the header in the DTS source directory. 14*5438d75fSJayesh Choudhary */ 15*5438d75fSJayesh Choudhary #warning "These bindings are deprecated. Instead, use the header in the DTS source directory." 16*5438d75fSJayesh Choudhary 17c65176fdSRoger Quadros /* J721E */ 18c65176fdSRoger Quadros 19c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 20c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 21c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 22c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 23c65176fdSRoger Quadros 24c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 25c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 26c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_USB3_0 0x2 27c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 28c65176fdSRoger Quadros 29c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 30c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 31c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 32c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 33c65176fdSRoger Quadros 34c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 35c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 36c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_USB3_1 0x2 37c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 38c65176fdSRoger Quadros 39c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 40c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 41c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 42c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 43c65176fdSRoger Quadros 44c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 45c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 46c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_USB3_1 0x2 47c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 48c65176fdSRoger Quadros 49c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 50c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 51c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 52c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 53c65176fdSRoger Quadros 54c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 55c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 56c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_USB3_0 0x2 57c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 58c65176fdSRoger Quadros 59c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_EDP_LANE0 0x0 60c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 61c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 62c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 63c65176fdSRoger Quadros 64c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_EDP_LANE1 0x0 65c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 66c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 67c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 68c65176fdSRoger Quadros 69c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_EDP_LANE2 0x0 70c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 71c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 72c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 73c65176fdSRoger Quadros 74c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_EDP_LANE3 0x0 75c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 76c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 77c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 78c65176fdSRoger Quadros 79ba90e0c9SRoger Quadros /* J7200 */ 80ba90e0c9SRoger Quadros 81ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 82ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 83ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 84ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 85ba90e0c9SRoger Quadros 86ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 87ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 88ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 89ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 90ba90e0c9SRoger Quadros 91ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 92ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 93ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 94ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 95ba90e0c9SRoger Quadros 96ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 97ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 98ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_USB 0x2 99ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 100ba90e0c9SRoger Quadros 1014709b21aSKishon Vijay Abraham I /* AM64 */ 1024709b21aSKishon Vijay Abraham I 1034709b21aSKishon Vijay Abraham I #define AM64_SERDES0_LANE0_PCIE0 0x0 1044709b21aSKishon Vijay Abraham I #define AM64_SERDES0_LANE0_USB 0x1 1054709b21aSKishon Vijay Abraham I 10604ce4a6bSAswath Govindraju /* J721S2 */ 10704ce4a6bSAswath Govindraju 10804ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 10904ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 11004ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 11104ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 11204ce4a6bSAswath Govindraju 11304ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 11404ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 11504ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_USB 0x2 11604ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 11704ce4a6bSAswath Govindraju 11804ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 11904ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 12004ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 12104ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 12204ce4a6bSAswath Govindraju 12304ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 12404ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 12504ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_USB 0x2 12604ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 12704ce4a6bSAswath Govindraju 1288258d997SMatt Ranostay /* J784S4 */ 1298258d997SMatt Ranostay 1308258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 1318258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 1328258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 1338258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 1348258d997SMatt Ranostay 1358258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 1368258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 1378258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 1388258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 1398258d997SMatt Ranostay 1408258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 1418258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 1428258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 1438258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 1448258d997SMatt Ranostay 1458258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 1468258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 1478258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_USB 0x2 1488258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 1498258d997SMatt Ranostay 1508258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 1518258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 1528258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 1538258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 1548258d997SMatt Ranostay 1558258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 1568258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 1578258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 1588258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 1598258d997SMatt Ranostay 1608258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 1618258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 1628258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 1638258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 1648258d997SMatt Ranostay 1658258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 1668258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 1678258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 1688258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 1698258d997SMatt Ranostay 1708258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 1718258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 1728258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 1738258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 1748258d997SMatt Ranostay 1758258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 1768258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 1778258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 1788258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 1798258d997SMatt Ranostay 1808258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 1818258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 1828258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 1838258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 1848258d997SMatt Ranostay 1858258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 1868258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 1878258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 1888258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 1898258d997SMatt Ranostay 190c65176fdSRoger Quadros #endif /* _DT_BINDINGS_MUX_TI_SERDES */ 191