1c65176fdSRoger Quadros /* SPDX-License-Identifier: GPL-2.0 */ 2c65176fdSRoger Quadros /* 3c65176fdSRoger Quadros * This header provides constants for SERDES MUX for TI SoCs 4c65176fdSRoger Quadros */ 5c65176fdSRoger Quadros 6c65176fdSRoger Quadros #ifndef _DT_BINDINGS_MUX_TI_SERDES 7c65176fdSRoger Quadros #define _DT_BINDINGS_MUX_TI_SERDES 8c65176fdSRoger Quadros 9c65176fdSRoger Quadros /* J721E */ 10c65176fdSRoger Quadros 11c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 12c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 13c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 14c65176fdSRoger Quadros #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 15c65176fdSRoger Quadros 16c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 17c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 18c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_USB3_0 0x2 19c65176fdSRoger Quadros #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 20c65176fdSRoger Quadros 21c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 22c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 23c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 24c65176fdSRoger Quadros #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 25c65176fdSRoger Quadros 26c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 27c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 28c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_USB3_1 0x2 29c65176fdSRoger Quadros #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 30c65176fdSRoger Quadros 31c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 32c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 33c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 34c65176fdSRoger Quadros #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 35c65176fdSRoger Quadros 36c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 37c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 38c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_USB3_1 0x2 39c65176fdSRoger Quadros #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 40c65176fdSRoger Quadros 41c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 42c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 43c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 44c65176fdSRoger Quadros #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 45c65176fdSRoger Quadros 46c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 47c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 48c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_USB3_0 0x2 49c65176fdSRoger Quadros #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 50c65176fdSRoger Quadros 51c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_EDP_LANE0 0x0 52c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 53c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 54c65176fdSRoger Quadros #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 55c65176fdSRoger Quadros 56c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_EDP_LANE1 0x0 57c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 58c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 59c65176fdSRoger Quadros #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 60c65176fdSRoger Quadros 61c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_EDP_LANE2 0x0 62c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 63c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 64c65176fdSRoger Quadros #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 65c65176fdSRoger Quadros 66c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_EDP_LANE3 0x0 67c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 68c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 69c65176fdSRoger Quadros #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 70c65176fdSRoger Quadros 71ba90e0c9SRoger Quadros /* J7200 */ 72ba90e0c9SRoger Quadros 73ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 74ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 75ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 76ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 77ba90e0c9SRoger Quadros 78ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 79ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 80ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 81ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 82ba90e0c9SRoger Quadros 83ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 84ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 85ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 86ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 87ba90e0c9SRoger Quadros 88ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 89ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 90ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_USB 0x2 91ba90e0c9SRoger Quadros #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 92ba90e0c9SRoger Quadros 934709b21aSKishon Vijay Abraham I /* AM64 */ 944709b21aSKishon Vijay Abraham I 954709b21aSKishon Vijay Abraham I #define AM64_SERDES0_LANE0_PCIE0 0x0 964709b21aSKishon Vijay Abraham I #define AM64_SERDES0_LANE0_USB 0x1 974709b21aSKishon Vijay Abraham I 9804ce4a6bSAswath Govindraju /* J721S2 */ 9904ce4a6bSAswath Govindraju 10004ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 10104ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 10204ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 10304ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 10404ce4a6bSAswath Govindraju 10504ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 10604ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 10704ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_USB 0x2 10804ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 10904ce4a6bSAswath Govindraju 11004ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 11104ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 11204ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 11304ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 11404ce4a6bSAswath Govindraju 11504ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 11604ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 11704ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_USB 0x2 11804ce4a6bSAswath Govindraju #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 11904ce4a6bSAswath Govindraju 120*8258d997SMatt Ranostay /* J784S4 */ 121*8258d997SMatt Ranostay 122*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 123*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 124*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 125*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 126*8258d997SMatt Ranostay 127*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 128*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 129*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 130*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 131*8258d997SMatt Ranostay 132*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 133*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 134*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 135*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 136*8258d997SMatt Ranostay 137*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 138*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 139*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_USB 0x2 140*8258d997SMatt Ranostay #define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 141*8258d997SMatt Ranostay 142*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 143*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 144*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 145*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 146*8258d997SMatt Ranostay 147*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 148*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 149*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 150*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 151*8258d997SMatt Ranostay 152*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 153*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 154*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 155*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 156*8258d997SMatt Ranostay 157*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 158*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 159*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 160*8258d997SMatt Ranostay #define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 161*8258d997SMatt Ranostay 162*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 163*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 164*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 165*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 166*8258d997SMatt Ranostay 167*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 168*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 169*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 170*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 171*8258d997SMatt Ranostay 172*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 173*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 174*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 175*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 176*8258d997SMatt Ranostay 177*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 178*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 179*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 180*8258d997SMatt Ranostay #define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 181*8258d997SMatt Ranostay 182c65176fdSRoger Quadros #endif /* _DT_BINDINGS_MUX_TI_SERDES */ 183