1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H 3 #define DT_BINDINGS_MEMORY_TEGRA114_MC_H 4 5 #define TEGRA_SWGROUP_PTC 0 6 #define TEGRA_SWGROUP_DC 1 7 #define TEGRA_SWGROUP_DCB 2 8 #define TEGRA_SWGROUP_EPP 3 9 #define TEGRA_SWGROUP_G2 4 10 #define TEGRA_SWGROUP_AVPC 5 11 #define TEGRA_SWGROUP_NV 6 12 #define TEGRA_SWGROUP_HDA 7 13 #define TEGRA_SWGROUP_HC 8 14 #define TEGRA_SWGROUP_MSENC 9 15 #define TEGRA_SWGROUP_PPCS 10 16 #define TEGRA_SWGROUP_VDE 11 17 #define TEGRA_SWGROUP_MPCORELP 12 18 #define TEGRA_SWGROUP_MPCORE 13 19 #define TEGRA_SWGROUP_VI 14 20 #define TEGRA_SWGROUP_ISP 15 21 #define TEGRA_SWGROUP_XUSB_HOST 16 22 #define TEGRA_SWGROUP_XUSB_DEV 17 23 #define TEGRA_SWGROUP_EMUCIF 18 24 #define TEGRA_SWGROUP_TSEC 19 25 26 #define TEGRA114_MC_RESET_AVPC 0 27 #define TEGRA114_MC_RESET_DC 1 28 #define TEGRA114_MC_RESET_DCB 2 29 #define TEGRA114_MC_RESET_EPP 3 30 #define TEGRA114_MC_RESET_2D 4 31 #define TEGRA114_MC_RESET_HC 5 32 #define TEGRA114_MC_RESET_HDA 6 33 #define TEGRA114_MC_RESET_ISP 7 34 #define TEGRA114_MC_RESET_MPCORE 8 35 #define TEGRA114_MC_RESET_MPCORELP 9 36 #define TEGRA114_MC_RESET_MPE 10 37 #define TEGRA114_MC_RESET_3D 11 38 #define TEGRA114_MC_RESET_3D2 12 39 #define TEGRA114_MC_RESET_PPCS 13 40 #define TEGRA114_MC_RESET_VDE 14 41 #define TEGRA114_MC_RESET_VI 15 42 43 #define TEGRA114_MC_PTCR 0 44 #define TEGRA114_MC_DISPLAY0A 1 45 #define TEGRA114_MC_DISPLAY0AB 2 46 #define TEGRA114_MC_DISPLAY0B 3 47 #define TEGRA114_MC_DISPLAY0BB 4 48 #define TEGRA114_MC_DISPLAY0C 5 49 #define TEGRA114_MC_DISPLAY0CB 6 50 #define TEGRA114_MC_DISPLAY1B 7 51 #define TEGRA114_MC_DISPLAY1BB 8 52 #define TEGRA114_MC_EPPUP 9 53 #define TEGRA114_MC_G2PR 10 54 #define TEGRA114_MC_G2SR 11 55 #define TEGRA114_MC_MPEUNIFBR 12 56 #define TEGRA114_MC_VIRUV 13 57 #define TEGRA114_MC_AFIR 14 58 #define TEGRA114_MC_AVPCARM7R 15 59 #define TEGRA114_MC_DISPLAYHC 16 60 #define TEGRA114_MC_DISPLAYHCB 17 61 #define TEGRA114_MC_FDCDRD 18 62 #define TEGRA114_MC_FDCDRD2 19 63 #define TEGRA114_MC_G2DR 20 64 #define TEGRA114_MC_HDAR 21 65 #define TEGRA114_MC_HOST1XDMAR 22 66 #define TEGRA114_MC_HOST1XR 23 67 #define TEGRA114_MC_IDXSRD 24 68 #define TEGRA114_MC_IDXSRD2 25 69 #define TEGRA114_MC_MPE_IPRED 26 70 #define TEGRA114_MC_MPEAMEMRD 27 71 #define TEGRA114_MC_MPECSRD 28 72 #define TEGRA114_MC_PPCSAHBDMAR 29 73 #define TEGRA114_MC_PPCSAHBSLVR 30 74 #define TEGRA114_MC_SATAR 31 75 #define TEGRA114_MC_TEXSRD 32 76 #define TEGRA114_MC_TEXSRD2 33 77 #define TEGRA114_MC_VDEBSEVR 34 78 #define TEGRA114_MC_VDEMBER 35 79 #define TEGRA114_MC_VDEMCER 36 80 #define TEGRA114_MC_VDETPER 37 81 #define TEGRA114_MC_MPCORELPR 38 82 #define TEGRA114_MC_MPCORER 39 83 #define TEGRA114_MC_EPPU 40 84 #define TEGRA114_MC_EPPV 41 85 #define TEGRA114_MC_EPPY 42 86 #define TEGRA114_MC_MPEUNIFBW 43 87 #define TEGRA114_MC_VIWSB 44 88 #define TEGRA114_MC_VIWU 45 89 #define TEGRA114_MC_VIWV 46 90 #define TEGRA114_MC_VIWY 47 91 #define TEGRA114_MC_G2DW 48 92 #define TEGRA114_MC_AFIW 49 93 #define TEGRA114_MC_AVPCARM7W 50 94 #define TEGRA114_MC_FDCDWR 51 95 #define TEGRA114_MC_FDCDWR2 52 96 #define TEGRA114_MC_HDAW 53 97 #define TEGRA114_MC_HOST1XW 54 98 #define TEGRA114_MC_ISPW 55 99 #define TEGRA114_MC_MPCORELPW 56 100 #define TEGRA114_MC_MPCOREW 57 101 #define TEGRA114_MC_MPECSWR 58 102 #define TEGRA114_MC_PPCSAHBDMAW 59 103 #define TEGRA114_MC_PPCSAHBSLVW 60 104 #define TEGRA114_MC_SATAW 61 105 #define TEGRA114_MC_VDEBSEVW 62 106 #define TEGRA114_MC_VDEDBGW 63 107 #define TEGRA114_MC_VDEMBEW 64 108 #define TEGRA114_MC_VDETPMW 65 109 110 #endif 111