150fa3cd3SYong Wu /* SPDX-License-Identifier: GPL-2.0 */ 250fa3cd3SYong Wu /* 350fa3cd3SYong Wu * Copyright (c) 2017 MediaTek Inc. 450fa3cd3SYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 550fa3cd3SYong Wu */ 6*ddd3e349SYong Wu #ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 7*ddd3e349SYong Wu #define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 850fa3cd3SYong Wu 95cf482f2SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 1050fa3cd3SYong Wu 1150fa3cd3SYong Wu #define M4U_LARB0_ID 0 1250fa3cd3SYong Wu #define M4U_LARB1_ID 1 1350fa3cd3SYong Wu #define M4U_LARB2_ID 2 1450fa3cd3SYong Wu #define M4U_LARB3_ID 3 1550fa3cd3SYong Wu #define M4U_LARB4_ID 4 1650fa3cd3SYong Wu #define M4U_LARB5_ID 5 1750fa3cd3SYong Wu #define M4U_LARB6_ID 6 1850fa3cd3SYong Wu #define M4U_LARB7_ID 7 1950fa3cd3SYong Wu #define M4U_LARB8_ID 8 2050fa3cd3SYong Wu #define M4U_LARB9_ID 9 2150fa3cd3SYong Wu 2250fa3cd3SYong Wu /* larb0 */ 2350fa3cd3SYong Wu #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 2450fa3cd3SYong Wu #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 2550fa3cd3SYong Wu #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 2650fa3cd3SYong Wu #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 2750fa3cd3SYong Wu #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 2850fa3cd3SYong Wu #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 2950fa3cd3SYong Wu #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 3050fa3cd3SYong Wu #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) 3150fa3cd3SYong Wu 3250fa3cd3SYong Wu /* larb1 */ 3350fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 3450fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 3550fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 3650fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 3750fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 3850fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 3950fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 4050fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 4150fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 4250fa3cd3SYong Wu #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 4350fa3cd3SYong Wu #define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) 4450fa3cd3SYong Wu 4550fa3cd3SYong Wu /* larb2 */ 4650fa3cd3SYong Wu #define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) 4750fa3cd3SYong Wu #define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) 4850fa3cd3SYong Wu #define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) 4950fa3cd3SYong Wu 5050fa3cd3SYong Wu /* larb3 */ 5150fa3cd3SYong Wu #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 5250fa3cd3SYong Wu #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 5350fa3cd3SYong Wu #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 5450fa3cd3SYong Wu #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 5550fa3cd3SYong Wu #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 5650fa3cd3SYong Wu #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) 5750fa3cd3SYong Wu #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) 5850fa3cd3SYong Wu #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) 5950fa3cd3SYong Wu #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) 6050fa3cd3SYong Wu 6150fa3cd3SYong Wu /* larb4 */ 6250fa3cd3SYong Wu #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 6350fa3cd3SYong Wu #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 6450fa3cd3SYong Wu #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) 6550fa3cd3SYong Wu #define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) 6650fa3cd3SYong Wu #define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) 6750fa3cd3SYong Wu #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) 6850fa3cd3SYong Wu #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) 6950fa3cd3SYong Wu 7050fa3cd3SYong Wu /* larb5 */ 7150fa3cd3SYong Wu #define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) 7250fa3cd3SYong Wu #define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) 7350fa3cd3SYong Wu #define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) 7450fa3cd3SYong Wu #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) 7550fa3cd3SYong Wu 7650fa3cd3SYong Wu /* larb6 */ 7750fa3cd3SYong Wu #define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) 7850fa3cd3SYong Wu #define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) 7950fa3cd3SYong Wu #define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) 8050fa3cd3SYong Wu #define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) 8150fa3cd3SYong Wu 8250fa3cd3SYong Wu /* larb7 */ 8350fa3cd3SYong Wu #define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) 8450fa3cd3SYong Wu #define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) 8550fa3cd3SYong Wu 8650fa3cd3SYong Wu /* larb8 */ 8750fa3cd3SYong Wu #define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) 8850fa3cd3SYong Wu #define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) 8950fa3cd3SYong Wu #define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) 9050fa3cd3SYong Wu 9150fa3cd3SYong Wu /* larb9 */ 9250fa3cd3SYong Wu #define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) 9350fa3cd3SYong Wu #define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) 9450fa3cd3SYong Wu 9550fa3cd3SYong Wu #endif 96