1*59a316fdSFabien Parent /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*59a316fdSFabien Parent /* 3*59a316fdSFabien Parent * Copyright (c) 2022 MediaTek Inc. 4*59a316fdSFabien Parent * Author: Yong Wu <yong.wu@mediatek.com> 5*59a316fdSFabien Parent */ 6*59a316fdSFabien Parent #ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ 7*59a316fdSFabien Parent #define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ 8*59a316fdSFabien Parent 9*59a316fdSFabien Parent #include <dt-bindings/memory/mtk-memory-port.h> 10*59a316fdSFabien Parent 11*59a316fdSFabien Parent #define M4U_LARB0_ID 0 12*59a316fdSFabien Parent #define M4U_LARB1_ID 1 13*59a316fdSFabien Parent #define M4U_LARB2_ID 2 14*59a316fdSFabien Parent #define M4U_LARB3_ID 3 15*59a316fdSFabien Parent 16*59a316fdSFabien Parent /* larb0 */ 17*59a316fdSFabien Parent #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 18*59a316fdSFabien Parent #define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1) 19*59a316fdSFabien Parent #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 20*59a316fdSFabien Parent #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) 21*59a316fdSFabien Parent #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) 22*59a316fdSFabien Parent #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 23*59a316fdSFabien Parent #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6) 24*59a316fdSFabien Parent #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 25*59a316fdSFabien Parent #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8) 26*59a316fdSFabien Parent #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) 27*59a316fdSFabien Parent #define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10) 28*59a316fdSFabien Parent #define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11) 29*59a316fdSFabien Parent 30*59a316fdSFabien Parent /* larb1 */ 31*59a316fdSFabien Parent #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0) 32*59a316fdSFabien Parent #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1) 33*59a316fdSFabien Parent #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2) 34*59a316fdSFabien Parent #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3) 35*59a316fdSFabien Parent #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4) 36*59a316fdSFabien Parent #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5) 37*59a316fdSFabien Parent #define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6) 38*59a316fdSFabien Parent #define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7) 39*59a316fdSFabien Parent #define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8) 40*59a316fdSFabien Parent #define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9) 41*59a316fdSFabien Parent #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10) 42*59a316fdSFabien Parent #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11) 43*59a316fdSFabien Parent #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12) 44*59a316fdSFabien Parent #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13) 45*59a316fdSFabien Parent #define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14) 46*59a316fdSFabien Parent #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15) 47*59a316fdSFabien Parent #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16) 48*59a316fdSFabien Parent #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17) 49*59a316fdSFabien Parent #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18) 50*59a316fdSFabien Parent 51*59a316fdSFabien Parent /* larb2 */ 52*59a316fdSFabien Parent #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) 53*59a316fdSFabien Parent #define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) 54*59a316fdSFabien Parent #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) 55*59a316fdSFabien Parent #define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3) 56*59a316fdSFabien Parent #define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) 57*59a316fdSFabien Parent #define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5) 58*59a316fdSFabien Parent #define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6) 59*59a316fdSFabien Parent #define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7) 60*59a316fdSFabien Parent #define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8) 61*59a316fdSFabien Parent #define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9) 62*59a316fdSFabien Parent #define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10) 63*59a316fdSFabien Parent #define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11) 64*59a316fdSFabien Parent #define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12) 65*59a316fdSFabien Parent #define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13) 66*59a316fdSFabien Parent #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14) 67*59a316fdSFabien Parent #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15) 68*59a316fdSFabien Parent #define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16) 69*59a316fdSFabien Parent #define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17) 70*59a316fdSFabien Parent #define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18) 71*59a316fdSFabien Parent #define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19) 72*59a316fdSFabien Parent #define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20) 73*59a316fdSFabien Parent #define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21) 74*59a316fdSFabien Parent #define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22) 75*59a316fdSFabien Parent #define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23) 76*59a316fdSFabien Parent 77*59a316fdSFabien Parent /* larb3 */ 78*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0) 79*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1) 80*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2) 81*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3) 82*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4) 83*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5) 84*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6) 85*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7) 86*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8) 87*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9) 88*59a316fdSFabien Parent #define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10) 89*59a316fdSFabien Parent 90*59a316fdSFabien Parent #endif 91