1*83268fa6SDhaval Shah // SPDX-License-Identifier: GPL-2.0 2df330515SLaurent Pinchart /* 3df330515SLaurent Pinchart * Xilinx Video IP Core 4df330515SLaurent Pinchart * 5df330515SLaurent Pinchart * Copyright (C) 2013-2015 Ideas on Board 6df330515SLaurent Pinchart * Copyright (C) 2013-2015 Xilinx, Inc. 7df330515SLaurent Pinchart * 8df330515SLaurent Pinchart * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 9df330515SLaurent Pinchart * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10df330515SLaurent Pinchart */ 11df330515SLaurent Pinchart 12df330515SLaurent Pinchart #ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 13df330515SLaurent Pinchart #define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 14df330515SLaurent Pinchart 15df330515SLaurent Pinchart /* 16df330515SLaurent Pinchart * Video format codes as defined in "AXI4-Stream Video IP and System Design 17df330515SLaurent Pinchart * Guide". 18df330515SLaurent Pinchart */ 19df330515SLaurent Pinchart #define XVIP_VF_YUV_422 0 20df330515SLaurent Pinchart #define XVIP_VF_YUV_444 1 21df330515SLaurent Pinchart #define XVIP_VF_RBG 2 22df330515SLaurent Pinchart #define XVIP_VF_YUV_420 3 23df330515SLaurent Pinchart #define XVIP_VF_YUVA_422 4 24df330515SLaurent Pinchart #define XVIP_VF_YUVA_444 5 25df330515SLaurent Pinchart #define XVIP_VF_RGBA 6 26df330515SLaurent Pinchart #define XVIP_VF_YUVA_420 7 27df330515SLaurent Pinchart #define XVIP_VF_YUVD_422 8 28df330515SLaurent Pinchart #define XVIP_VF_YUVD_444 9 29df330515SLaurent Pinchart #define XVIP_VF_RGBD 10 30df330515SLaurent Pinchart #define XVIP_VF_YUVD_420 11 31df330515SLaurent Pinchart #define XVIP_VF_MONO_SENSOR 12 32df330515SLaurent Pinchart #define XVIP_VF_CUSTOM2 13 33df330515SLaurent Pinchart #define XVIP_VF_CUSTOM3 14 34df330515SLaurent Pinchart #define XVIP_VF_CUSTOM4 15 35df330515SLaurent Pinchart 36df330515SLaurent Pinchart #endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */ 37