1*5350a237SEddie James /* SPDX-License-Identifier: GPL-2.0+ */ 2*5350a237SEddie James 3*5350a237SEddie James #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ 4*5350a237SEddie James #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ 5*5350a237SEddie James 6*5350a237SEddie James #define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0 7*5350a237SEddie James #define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1 8*5350a237SEddie James 9*5350a237SEddie James #define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2 10*5350a237SEddie James #define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3 11*5350a237SEddie James #define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4 12*5350a237SEddie James #define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5 13*5350a237SEddie James #define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6 14*5350a237SEddie James 15*5350a237SEddie James #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2 16*5350a237SEddie James #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3 17*5350a237SEddie James #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4 18*5350a237SEddie James #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5 19*5350a237SEddie James 20*5350a237SEddie James #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 21*5350a237SEddie James #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 22*5350a237SEddie James 23*5350a237SEddie James #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ 24