1d061864bSStephen Warren /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 24be505d4SStephen Warren /* 34be505d4SStephen Warren * This header provides constants for the ARM GIC. 44be505d4SStephen Warren */ 54be505d4SStephen Warren 64be505d4SStephen Warren #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 74be505d4SStephen Warren #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 84be505d4SStephen Warren 94be505d4SStephen Warren #include <dt-bindings/interrupt-controller/irq.h> 104be505d4SStephen Warren 11d6613aa7SGeert Uytterhoeven /* interrupt specifier cell 0 */ 124be505d4SStephen Warren 134be505d4SStephen Warren #define GIC_SPI 0 144be505d4SStephen Warren #define GIC_PPI 1 15*58b3ac24SNikunj Kela #define GIC_ESPI 2 16*58b3ac24SNikunj Kela #define GIC_EPPI 3 174be505d4SStephen Warren 184be505d4SStephen Warren /* 194be505d4SStephen Warren * Interrupt specifier cell 2. 20d6613aa7SGeert Uytterhoeven * The flags in irq.h are valid, plus those below. 214be505d4SStephen Warren */ 224be505d4SStephen Warren #define GIC_CPU_MASK_RAW(x) ((x) << 8) 234be505d4SStephen Warren #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 244be505d4SStephen Warren 254be505d4SStephen Warren #endif 26