xref: /linux/include/dt-bindings/interconnect/qcom,shikra.h (revision efe86f088f48f18c27b648e5724048947f3b7fb4)
1*0f90f883SRaviteja Laggyshetty /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*0f90f883SRaviteja Laggyshetty /*
3*0f90f883SRaviteja Laggyshetty  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4*0f90f883SRaviteja Laggyshetty  */
5*0f90f883SRaviteja Laggyshetty 
6*0f90f883SRaviteja Laggyshetty #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
7*0f90f883SRaviteja Laggyshetty #define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
8*0f90f883SRaviteja Laggyshetty 
9*0f90f883SRaviteja Laggyshetty #define MASTER_QUP_CORE_0			0
10*0f90f883SRaviteja Laggyshetty #define SLAVE_QUP_CORE_0			1
11*0f90f883SRaviteja Laggyshetty 
12*0f90f883SRaviteja Laggyshetty #define SNOC_CNOC_MAS				0
13*0f90f883SRaviteja Laggyshetty #define MASTER_QDSS_DAP				1
14*0f90f883SRaviteja Laggyshetty #define SLAVE_AHB2PHY_USB			2
15*0f90f883SRaviteja Laggyshetty #define SLAVE_APSS_THROTTLE_CFG			3
16*0f90f883SRaviteja Laggyshetty #define SLAVE_AUDIO				4
17*0f90f883SRaviteja Laggyshetty #define SLAVE_BOOT_ROM				5
18*0f90f883SRaviteja Laggyshetty #define SLAVE_CAMERA_NRT_THROTTLE_CFG		6
19*0f90f883SRaviteja Laggyshetty #define SLAVE_CAMERA_CFG			7
20*0f90f883SRaviteja Laggyshetty #define SLAVE_CDSP_THROTTLE_CFG			8
21*0f90f883SRaviteja Laggyshetty #define SLAVE_CLK_CTL				9
22*0f90f883SRaviteja Laggyshetty #define SLAVE_DSP_CFG				10
23*0f90f883SRaviteja Laggyshetty #define SLAVE_RBCPR_CX_CFG			11
24*0f90f883SRaviteja Laggyshetty #define SLAVE_RBCPR_MX_CFG			12
25*0f90f883SRaviteja Laggyshetty #define SLAVE_CRYPTO_0_CFG			13
26*0f90f883SRaviteja Laggyshetty #define SLAVE_DDR_SS_CFG			14
27*0f90f883SRaviteja Laggyshetty #define SLAVE_DISPLAY_CFG			15
28*0f90f883SRaviteja Laggyshetty #define SLAVE_EMAC0_CFG				16
29*0f90f883SRaviteja Laggyshetty #define SLAVE_EMAC1_CFG				17
30*0f90f883SRaviteja Laggyshetty #define SLAVE_GPU_CFG				18
31*0f90f883SRaviteja Laggyshetty #define SLAVE_GPU_THROTTLE_CFG			19
32*0f90f883SRaviteja Laggyshetty #define SLAVE_HWKM				20
33*0f90f883SRaviteja Laggyshetty #define SLAVE_IMEM_CFG				21
34*0f90f883SRaviteja Laggyshetty #define SLAVE_MAPSS				22
35*0f90f883SRaviteja Laggyshetty #define SLAVE_MDSP_MPU_CFG			23
36*0f90f883SRaviteja Laggyshetty #define SLAVE_MESSAGE_RAM			24
37*0f90f883SRaviteja Laggyshetty #define SLAVE_MSS				25
38*0f90f883SRaviteja Laggyshetty #define SLAVE_PCIE_CFG				26
39*0f90f883SRaviteja Laggyshetty #define SLAVE_PDM				27
40*0f90f883SRaviteja Laggyshetty #define SLAVE_PIMEM_CFG				28
41*0f90f883SRaviteja Laggyshetty #define SLAVE_PKA_WRAPPER_CFG			29
42*0f90f883SRaviteja Laggyshetty #define SLAVE_PMIC_ARB				30
43*0f90f883SRaviteja Laggyshetty #define SLAVE_QDSS_CFG				31
44*0f90f883SRaviteja Laggyshetty #define SLAVE_QM_CFG				32
45*0f90f883SRaviteja Laggyshetty #define SLAVE_QM_MPU_CFG			33
46*0f90f883SRaviteja Laggyshetty #define SLAVE_QPIC				34
47*0f90f883SRaviteja Laggyshetty #define SLAVE_QUP_0				35
48*0f90f883SRaviteja Laggyshetty #define SLAVE_RPM				36
49*0f90f883SRaviteja Laggyshetty #define SLAVE_SDCC_1				37
50*0f90f883SRaviteja Laggyshetty #define SLAVE_SDCC_2				38
51*0f90f883SRaviteja Laggyshetty #define SLAVE_SECURITY				39
52*0f90f883SRaviteja Laggyshetty #define SLAVE_SNOC_CFG				40
53*0f90f883SRaviteja Laggyshetty #define SNOC_SF_THROTTLE_CFG			41
54*0f90f883SRaviteja Laggyshetty #define SLAVE_TLMM				42
55*0f90f883SRaviteja Laggyshetty #define SLAVE_TSCSS				43
56*0f90f883SRaviteja Laggyshetty #define SLAVE_USB2				44
57*0f90f883SRaviteja Laggyshetty #define SLAVE_USB3				45
58*0f90f883SRaviteja Laggyshetty #define SLAVE_VENUS_CFG				46
59*0f90f883SRaviteja Laggyshetty #define SLAVE_VENUS_THROTTLE_CFG		47
60*0f90f883SRaviteja Laggyshetty #define SLAVE_VSENSE_CTRL_CFG			48
61*0f90f883SRaviteja Laggyshetty #define SLAVE_SERVICE_CNOC			49
62*0f90f883SRaviteja Laggyshetty 
63*0f90f883SRaviteja Laggyshetty #define MASTER_LLCC				0
64*0f90f883SRaviteja Laggyshetty #define SLAVE_EBI_CH0				1
65*0f90f883SRaviteja Laggyshetty 
66*0f90f883SRaviteja Laggyshetty #define MASTER_GRAPHICS_3D			0
67*0f90f883SRaviteja Laggyshetty #define MASTER_MNOC_HF_MEM_NOC			1
68*0f90f883SRaviteja Laggyshetty #define MASTER_ANOC_PCIE_MEM_NOC		2
69*0f90f883SRaviteja Laggyshetty #define MASTER_SNOC_SF_MEM_NOC			3
70*0f90f883SRaviteja Laggyshetty #define MASTER_AMPSS_M0				4
71*0f90f883SRaviteja Laggyshetty #define MASTER_SYS_TCU				5
72*0f90f883SRaviteja Laggyshetty #define SLAVE_LLCC				6
73*0f90f883SRaviteja Laggyshetty #define SLAVE_MEMNOC_SNOC			7
74*0f90f883SRaviteja Laggyshetty #define SLAVE_MEM_NOC_PCIE_SNOC			8
75*0f90f883SRaviteja Laggyshetty 
76*0f90f883SRaviteja Laggyshetty #define MASTER_CAMNOC_SF			0
77*0f90f883SRaviteja Laggyshetty #define MASTER_VIDEO_P0				1
78*0f90f883SRaviteja Laggyshetty #define MASTER_VIDEO_PROC			2
79*0f90f883SRaviteja Laggyshetty #define SLAVE_MMNRT_VIRT			3
80*0f90f883SRaviteja Laggyshetty 
81*0f90f883SRaviteja Laggyshetty #define MASTER_CAMNOC_HF			0
82*0f90f883SRaviteja Laggyshetty #define MASTER_MDP_PORT0			1
83*0f90f883SRaviteja Laggyshetty #define MASTER_MMRT_VIRT			2
84*0f90f883SRaviteja Laggyshetty #define SLAVE_MM_MEMNOC				3
85*0f90f883SRaviteja Laggyshetty 
86*0f90f883SRaviteja Laggyshetty #define MASTER_SNOC_CFG				0
87*0f90f883SRaviteja Laggyshetty #define MASTER_TIC				1
88*0f90f883SRaviteja Laggyshetty #define MASTER_ANOC_SNOC			2
89*0f90f883SRaviteja Laggyshetty #define MASTER_MEMNOC_PCIE			3
90*0f90f883SRaviteja Laggyshetty #define MASTER_MEMNOC_SNOC			4
91*0f90f883SRaviteja Laggyshetty #define MASTER_PIMEM				5
92*0f90f883SRaviteja Laggyshetty #define MASTER_PCIE2_0				6
93*0f90f883SRaviteja Laggyshetty #define MASTER_QDSS_BAM				7
94*0f90f883SRaviteja Laggyshetty #define MASTER_QPIC				8
95*0f90f883SRaviteja Laggyshetty #define MASTER_QUP_0				9
96*0f90f883SRaviteja Laggyshetty #define CNOC_SNOC_MAS				10
97*0f90f883SRaviteja Laggyshetty #define MASTER_AUDIO				11
98*0f90f883SRaviteja Laggyshetty #define MASTER_EMAC_0				12
99*0f90f883SRaviteja Laggyshetty #define MASTER_EMAC_1				13
100*0f90f883SRaviteja Laggyshetty #define MASTER_QDSS_ETR				14
101*0f90f883SRaviteja Laggyshetty #define MASTER_SDCC_1				15
102*0f90f883SRaviteja Laggyshetty #define MASTER_SDCC_2				16
103*0f90f883SRaviteja Laggyshetty #define MASTER_USB2_0				17
104*0f90f883SRaviteja Laggyshetty #define MASTER_USB3				18
105*0f90f883SRaviteja Laggyshetty #define MASTER_CRYPTO_CORE0			19
106*0f90f883SRaviteja Laggyshetty #define SLAVE_APPSS				20
107*0f90f883SRaviteja Laggyshetty #define SLAVE_MCUSS				21
108*0f90f883SRaviteja Laggyshetty #define SLAVE_WCSS				22
109*0f90f883SRaviteja Laggyshetty #define SLAVE_MEMNOC_SF				23
110*0f90f883SRaviteja Laggyshetty #define SNOC_CNOC_SLV				24
111*0f90f883SRaviteja Laggyshetty #define SLAVE_BOOTIMEM				25
112*0f90f883SRaviteja Laggyshetty #define SLAVE_OCIMEM				26
113*0f90f883SRaviteja Laggyshetty #define SLAVE_PIMEM				27
114*0f90f883SRaviteja Laggyshetty #define SLAVE_SERVICE_SNOC			28
115*0f90f883SRaviteja Laggyshetty #define SLAVE_PCIE2_0				29
116*0f90f883SRaviteja Laggyshetty #define SLAVE_QDSS_STM				30
117*0f90f883SRaviteja Laggyshetty #define SLAVE_TCU				31
118*0f90f883SRaviteja Laggyshetty #define SLAVE_PCIE_MEMNOC			32
119*0f90f883SRaviteja Laggyshetty #define SLAVE_ANOC_SNOC				33
120*0f90f883SRaviteja Laggyshetty 
121*0f90f883SRaviteja Laggyshetty #endif
122