1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS8300_H 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_QCS8300_H 8 9 #define MASTER_QUP_3 0 10 #define MASTER_EMAC 1 11 #define MASTER_SDC 2 12 #define MASTER_UFS_MEM 3 13 #define MASTER_USB2 4 14 #define MASTER_USB3_0 5 15 #define SLAVE_A1NOC_SNOC 6 16 17 #define MASTER_QDSS_BAM 0 18 #define MASTER_QUP_0 1 19 #define MASTER_QUP_1 2 20 #define MASTER_CNOC_A2NOC 3 21 #define MASTER_CRYPTO_CORE0 4 22 #define MASTER_CRYPTO_CORE1 5 23 #define MASTER_IPA 6 24 #define MASTER_QDSS_ETR_0 7 25 #define MASTER_QDSS_ETR_1 8 26 #define SLAVE_A2NOC_SNOC 9 27 28 #define MASTER_QUP_CORE_0 0 29 #define MASTER_QUP_CORE_1 1 30 #define MASTER_QUP_CORE_3 2 31 #define SLAVE_QUP_CORE_0 3 32 #define SLAVE_QUP_CORE_1 4 33 #define SLAVE_QUP_CORE_3 5 34 35 #define MASTER_GEM_NOC_CNOC 0 36 #define MASTER_GEM_NOC_PCIE_SNOC 1 37 #define SLAVE_AHB2PHY_2 2 38 #define SLAVE_AHB2PHY_3 3 39 #define SLAVE_ANOC_THROTTLE_CFG 4 40 #define SLAVE_AOSS 5 41 #define SLAVE_APPSS 6 42 #define SLAVE_BOOT_ROM 7 43 #define SLAVE_CAMERA_CFG 8 44 #define SLAVE_CAMERA_NRT_THROTTLE_CFG 9 45 #define SLAVE_CAMERA_RT_THROTTLE_CFG 10 46 #define SLAVE_CLK_CTL 11 47 #define SLAVE_CDSP_CFG 12 48 #define SLAVE_RBCPR_CX_CFG 13 49 #define SLAVE_RBCPR_MMCX_CFG 14 50 #define SLAVE_RBCPR_MX_CFG 15 51 #define SLAVE_CPR_NSPCX 16 52 #define SLAVE_CPR_NSPHMX 17 53 #define SLAVE_CRYPTO_0_CFG 18 54 #define SLAVE_CX_RDPM 19 55 #define SLAVE_DISPLAY_CFG 20 56 #define SLAVE_DISPLAY_RT_THROTTLE_CFG 21 57 #define SLAVE_EMAC_CFG 22 58 #define SLAVE_GP_DSP0_CFG 23 59 #define SLAVE_GPDSP0_THROTTLE_CFG 24 60 #define SLAVE_GPU_TCU_THROTTLE_CFG 25 61 #define SLAVE_GFX3D_CFG 26 62 #define SLAVE_HWKM 27 63 #define SLAVE_IMEM_CFG 28 64 #define SLAVE_IPA_CFG 29 65 #define SLAVE_IPC_ROUTER_CFG 30 66 #define SLAVE_LPASS 31 67 #define SLAVE_LPASS_THROTTLE_CFG 32 68 #define SLAVE_MX_RDPM 33 69 #define SLAVE_MXC_RDPM 34 70 #define SLAVE_PCIE_0_CFG 35 71 #define SLAVE_PCIE_1_CFG 36 72 #define SLAVE_PCIE_TCU_THROTTLE_CFG 37 73 #define SLAVE_PCIE_THROTTLE_CFG 38 74 #define SLAVE_PDM 39 75 #define SLAVE_PIMEM_CFG 40 76 #define SLAVE_PKA_WRAPPER_CFG 41 77 #define SLAVE_QDSS_CFG 42 78 #define SLAVE_QM_CFG 43 79 #define SLAVE_QM_MPU_CFG 44 80 #define SLAVE_QUP_0 45 81 #define SLAVE_QUP_1 46 82 #define SLAVE_QUP_3 47 83 #define SLAVE_SAIL_THROTTLE_CFG 48 84 #define SLAVE_SDC1 49 85 #define SLAVE_SECURITY 50 86 #define SLAVE_SNOC_THROTTLE_CFG 51 87 #define SLAVE_TCSR 52 88 #define SLAVE_TLMM 53 89 #define SLAVE_TSC_CFG 54 90 #define SLAVE_UFS_MEM_CFG 55 91 #define SLAVE_USB2 56 92 #define SLAVE_USB3_0 57 93 #define SLAVE_VENUS_CFG 58 94 #define SLAVE_VENUS_CVP_THROTTLE_CFG 59 95 #define SLAVE_VENUS_V_CPU_THROTTLE_CFG 60 96 #define SLAVE_VENUS_VCODEC_THROTTLE_CFG 61 97 #define SLAVE_DDRSS_CFG 62 98 #define SLAVE_GPDSP_NOC_CFG 63 99 #define SLAVE_CNOC_MNOC_HF_CFG 64 100 #define SLAVE_CNOC_MNOC_SF_CFG 65 101 #define SLAVE_PCIE_ANOC_CFG 66 102 #define SLAVE_SNOC_CFG 67 103 #define SLAVE_BOOT_IMEM 68 104 #define SLAVE_IMEM 69 105 #define SLAVE_PIMEM 70 106 #define SLAVE_PCIE_0 71 107 #define SLAVE_PCIE_1 72 108 #define SLAVE_QDSS_STM 73 109 #define SLAVE_TCU 74 110 111 #define MASTER_CNOC_DC_NOC 0 112 #define SLAVE_LLCC_CFG 1 113 #define SLAVE_GEM_NOC_CFG 2 114 115 #define MASTER_GPU_TCU 0 116 #define MASTER_PCIE_TCU 1 117 #define MASTER_SYS_TCU 2 118 #define MASTER_APPSS_PROC 3 119 #define MASTER_COMPUTE_NOC 4 120 #define MASTER_GEM_NOC_CFG 5 121 #define MASTER_GPDSP_SAIL 6 122 #define MASTER_GFX3D 7 123 #define MASTER_MNOC_HF_MEM_NOC 8 124 #define MASTER_MNOC_SF_MEM_NOC 9 125 #define MASTER_ANOC_PCIE_GEM_NOC 10 126 #define MASTER_SNOC_GC_MEM_NOC 11 127 #define MASTER_SNOC_SF_MEM_NOC 12 128 #define SLAVE_GEM_NOC_CNOC 13 129 #define SLAVE_LLCC 14 130 #define SLAVE_GEM_NOC_PCIE_CNOC 15 131 #define SLAVE_SERVICE_GEM_NOC_1 16 132 #define SLAVE_SERVICE_GEM_NOC_2 17 133 #define SLAVE_SERVICE_GEM_NOC 18 134 #define SLAVE_SERVICE_GEM_NOC2 19 135 136 #define MASTER_SAILSS_MD0 0 137 #define MASTER_DSP0 1 138 #define SLAVE_GP_DSP_SAIL_NOC 2 139 140 #define MASTER_CNOC_LPASS_AG_NOC 0 141 #define MASTER_LPASS_PROC 1 142 #define SLAVE_LPASS_CORE_CFG 2 143 #define SLAVE_LPASS_LPI_CFG 3 144 #define SLAVE_LPASS_MPU_CFG 4 145 #define SLAVE_LPASS_TOP_CFG 5 146 #define SLAVE_LPASS_SNOC 6 147 #define SLAVE_SERVICES_LPASS_AML_NOC 7 148 #define SLAVE_SERVICE_LPASS_AG_NOC 8 149 150 #define MASTER_LLCC 0 151 #define SLAVE_EBI1 1 152 153 #define MASTER_CAMNOC_HF 0 154 #define MASTER_CAMNOC_ICP 1 155 #define MASTER_CAMNOC_SF 2 156 #define MASTER_MDP0 3 157 #define MASTER_MDP1 4 158 #define MASTER_CNOC_MNOC_HF_CFG 5 159 #define MASTER_CNOC_MNOC_SF_CFG 6 160 #define MASTER_VIDEO_P0 7 161 #define MASTER_VIDEO_PROC 8 162 #define MASTER_VIDEO_V_PROC 9 163 #define SLAVE_MNOC_HF_MEM_NOC 10 164 #define SLAVE_MNOC_SF_MEM_NOC 11 165 #define SLAVE_SERVICE_MNOC_HF 12 166 #define SLAVE_SERVICE_MNOC_SF 13 167 168 #define MASTER_CDSP_NOC_CFG 0 169 #define MASTER_CDSP_PROC 1 170 #define SLAVE_HCP_A 2 171 #define SLAVE_CDSP_MEM_NOC 3 172 #define SLAVE_SERVICE_NSP_NOC 4 173 174 #define MASTER_PCIE_0 0 175 #define MASTER_PCIE_1 1 176 #define SLAVE_ANOC_PCIE_GEM_NOC 2 177 178 #define MASTER_GIC_AHB 0 179 #define MASTER_A1NOC_SNOC 1 180 #define MASTER_A2NOC_SNOC 2 181 #define MASTER_LPASS_ANOC 3 182 #define MASTER_SNOC_CFG 4 183 #define MASTER_PIMEM 5 184 #define MASTER_GIC 6 185 #define SLAVE_SNOC_GEM_NOC_GC 7 186 #define SLAVE_SNOC_GEM_NOC_SF 8 187 #define SLAVE_SERVICE_SNOC 9 188 189 #endif 190