1*7463f5adSRaviteja Laggyshetty /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*7463f5adSRaviteja Laggyshetty /* 3*7463f5adSRaviteja Laggyshetty * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*7463f5adSRaviteja Laggyshetty */ 5*7463f5adSRaviteja Laggyshetty 6*7463f5adSRaviteja Laggyshetty #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H 7*7463f5adSRaviteja Laggyshetty #define __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H 8*7463f5adSRaviteja Laggyshetty 9*7463f5adSRaviteja Laggyshetty #define MASTER_QSPI_0 0 10*7463f5adSRaviteja Laggyshetty #define MASTER_CRYPTO 1 11*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_1 2 12*7463f5adSRaviteja Laggyshetty #define MASTER_SDCC_4 3 13*7463f5adSRaviteja Laggyshetty #define MASTER_UFS_MEM 4 14*7463f5adSRaviteja Laggyshetty #define MASTER_USB3 5 15*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_2 6 16*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_3 7 17*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_4 8 18*7463f5adSRaviteja Laggyshetty #define MASTER_IPA 9 19*7463f5adSRaviteja Laggyshetty #define MASTER_SOCCP_PROC 10 20*7463f5adSRaviteja Laggyshetty #define MASTER_SP 11 21*7463f5adSRaviteja Laggyshetty #define MASTER_QDSS_ETR 12 22*7463f5adSRaviteja Laggyshetty #define MASTER_QDSS_ETR_1 13 23*7463f5adSRaviteja Laggyshetty #define MASTER_SDCC_2 14 24*7463f5adSRaviteja Laggyshetty #define SLAVE_A1NOC_SNOC 15 25*7463f5adSRaviteja Laggyshetty #define SLAVE_A2NOC_SNOC 16 26*7463f5adSRaviteja Laggyshetty 27*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_CORE_0 0 28*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_CORE_1 1 29*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_CORE_2 2 30*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_CORE_3 3 31*7463f5adSRaviteja Laggyshetty #define MASTER_QUP_CORE_4 4 32*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_CORE_0 5 33*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_CORE_1 6 34*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_CORE_2 7 35*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_CORE_3 8 36*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_CORE_4 9 37*7463f5adSRaviteja Laggyshetty 38*7463f5adSRaviteja Laggyshetty #define MASTER_CNOC_CFG 0 39*7463f5adSRaviteja Laggyshetty #define SLAVE_AHB2PHY_SOUTH 1 40*7463f5adSRaviteja Laggyshetty #define SLAVE_AHB2PHY_NORTH 2 41*7463f5adSRaviteja Laggyshetty #define SLAVE_CAMERA_CFG 3 42*7463f5adSRaviteja Laggyshetty #define SLAVE_CLK_CTL 4 43*7463f5adSRaviteja Laggyshetty #define SLAVE_CRYPTO_0_CFG 5 44*7463f5adSRaviteja Laggyshetty #define SLAVE_DISPLAY_CFG 6 45*7463f5adSRaviteja Laggyshetty #define SLAVE_EVA_CFG 7 46*7463f5adSRaviteja Laggyshetty #define SLAVE_GFX3D_CFG 8 47*7463f5adSRaviteja Laggyshetty #define SLAVE_I2C 9 48*7463f5adSRaviteja Laggyshetty #define SLAVE_I3C_IBI0_CFG 10 49*7463f5adSRaviteja Laggyshetty #define SLAVE_I3C_IBI1_CFG 11 50*7463f5adSRaviteja Laggyshetty #define SLAVE_IMEM_CFG 12 51*7463f5adSRaviteja Laggyshetty #define SLAVE_IPC_ROUTER_CFG 13 52*7463f5adSRaviteja Laggyshetty #define SLAVE_CNOC_MSS 14 53*7463f5adSRaviteja Laggyshetty #define SLAVE_PCIE_CFG 15 54*7463f5adSRaviteja Laggyshetty #define SLAVE_PRNG 16 55*7463f5adSRaviteja Laggyshetty #define SLAVE_QDSS_CFG 17 56*7463f5adSRaviteja Laggyshetty #define SLAVE_QSPI_0 18 57*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_1 19 58*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_2 20 59*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_3 21 60*7463f5adSRaviteja Laggyshetty #define SLAVE_QUP_4 22 61*7463f5adSRaviteja Laggyshetty #define SLAVE_SDCC_2 23 62*7463f5adSRaviteja Laggyshetty #define SLAVE_SDCC_4 24 63*7463f5adSRaviteja Laggyshetty #define SLAVE_SPSS_CFG 25 64*7463f5adSRaviteja Laggyshetty #define SLAVE_TCSR 26 65*7463f5adSRaviteja Laggyshetty #define SLAVE_TLMM 27 66*7463f5adSRaviteja Laggyshetty #define SLAVE_UFS_MEM_CFG 28 67*7463f5adSRaviteja Laggyshetty #define SLAVE_USB3 29 68*7463f5adSRaviteja Laggyshetty #define SLAVE_VENUS_CFG 30 69*7463f5adSRaviteja Laggyshetty #define SLAVE_VSENSE_CTRL_CFG 31 70*7463f5adSRaviteja Laggyshetty #define SLAVE_CNOC_MNOC_CFG 32 71*7463f5adSRaviteja Laggyshetty #define SLAVE_PCIE_ANOC_CFG 33 72*7463f5adSRaviteja Laggyshetty #define SLAVE_QDSS_STM 34 73*7463f5adSRaviteja Laggyshetty #define SLAVE_TCU 35 74*7463f5adSRaviteja Laggyshetty 75*7463f5adSRaviteja Laggyshetty #define MASTER_GEM_NOC_CNOC 0 76*7463f5adSRaviteja Laggyshetty #define MASTER_GEM_NOC_PCIE_SNOC 1 77*7463f5adSRaviteja Laggyshetty #define SLAVE_AOSS 2 78*7463f5adSRaviteja Laggyshetty #define SLAVE_IPA_CFG 3 79*7463f5adSRaviteja Laggyshetty #define SLAVE_IPC_ROUTER_FENCE 4 80*7463f5adSRaviteja Laggyshetty #define SLAVE_SOCCP 5 81*7463f5adSRaviteja Laggyshetty #define SLAVE_TME_CFG 6 82*7463f5adSRaviteja Laggyshetty #define SLAVE_APPSS 7 83*7463f5adSRaviteja Laggyshetty #define SLAVE_CNOC_CFG 8 84*7463f5adSRaviteja Laggyshetty #define SLAVE_DDRSS_CFG 9 85*7463f5adSRaviteja Laggyshetty #define SLAVE_BOOT_IMEM 10 86*7463f5adSRaviteja Laggyshetty #define SLAVE_IMEM 11 87*7463f5adSRaviteja Laggyshetty #define SLAVE_PCIE_0 12 88*7463f5adSRaviteja Laggyshetty 89*7463f5adSRaviteja Laggyshetty #define MASTER_GPU_TCU 0 90*7463f5adSRaviteja Laggyshetty #define MASTER_SYS_TCU 1 91*7463f5adSRaviteja Laggyshetty #define MASTER_APPSS_PROC 2 92*7463f5adSRaviteja Laggyshetty #define MASTER_GFX3D 3 93*7463f5adSRaviteja Laggyshetty #define MASTER_LPASS_GEM_NOC 4 94*7463f5adSRaviteja Laggyshetty #define MASTER_MSS_PROC 5 95*7463f5adSRaviteja Laggyshetty #define MASTER_MNOC_HF_MEM_NOC 6 96*7463f5adSRaviteja Laggyshetty #define MASTER_MNOC_SF_MEM_NOC 7 97*7463f5adSRaviteja Laggyshetty #define MASTER_COMPUTE_NOC 8 98*7463f5adSRaviteja Laggyshetty #define MASTER_ANOC_PCIE_GEM_NOC 9 99*7463f5adSRaviteja Laggyshetty #define MASTER_QPACE 10 100*7463f5adSRaviteja Laggyshetty #define MASTER_SNOC_SF_MEM_NOC 11 101*7463f5adSRaviteja Laggyshetty #define MASTER_WLAN_Q6 12 102*7463f5adSRaviteja Laggyshetty #define MASTER_GIC 13 103*7463f5adSRaviteja Laggyshetty #define SLAVE_GEM_NOC_CNOC 14 104*7463f5adSRaviteja Laggyshetty #define SLAVE_LLCC 15 105*7463f5adSRaviteja Laggyshetty #define SLAVE_MEM_NOC_PCIE_SNOC 16 106*7463f5adSRaviteja Laggyshetty 107*7463f5adSRaviteja Laggyshetty #define MASTER_LPIAON_NOC 0 108*7463f5adSRaviteja Laggyshetty #define SLAVE_LPASS_GEM_NOC 1 109*7463f5adSRaviteja Laggyshetty 110*7463f5adSRaviteja Laggyshetty #define MASTER_LPASS_LPINOC 0 111*7463f5adSRaviteja Laggyshetty #define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 112*7463f5adSRaviteja Laggyshetty 113*7463f5adSRaviteja Laggyshetty #define MASTER_LPASS_PROC 0 114*7463f5adSRaviteja Laggyshetty #define SLAVE_LPICX_NOC_LPIAON_NOC 1 115*7463f5adSRaviteja Laggyshetty 116*7463f5adSRaviteja Laggyshetty #define MASTER_LLCC 0 117*7463f5adSRaviteja Laggyshetty #define SLAVE_EBI1 1 118*7463f5adSRaviteja Laggyshetty 119*7463f5adSRaviteja Laggyshetty #define MASTER_CAMNOC_HF 0 120*7463f5adSRaviteja Laggyshetty #define MASTER_CAMNOC_NRT_ICP_SF 1 121*7463f5adSRaviteja Laggyshetty #define MASTER_CAMNOC_RT_CDM_SF 2 122*7463f5adSRaviteja Laggyshetty #define MASTER_CAMNOC_SF 3 123*7463f5adSRaviteja Laggyshetty #define MASTER_MDP 4 124*7463f5adSRaviteja Laggyshetty #define MASTER_MDSS_DCP 5 125*7463f5adSRaviteja Laggyshetty #define MASTER_CDSP_HCP 6 126*7463f5adSRaviteja Laggyshetty #define MASTER_VIDEO_CV_PROC 7 127*7463f5adSRaviteja Laggyshetty #define MASTER_VIDEO_EVA 8 128*7463f5adSRaviteja Laggyshetty #define MASTER_VIDEO_MVP 9 129*7463f5adSRaviteja Laggyshetty #define MASTER_VIDEO_V_PROC 10 130*7463f5adSRaviteja Laggyshetty #define MASTER_CNOC_MNOC_CFG 11 131*7463f5adSRaviteja Laggyshetty #define SLAVE_MNOC_HF_MEM_NOC 12 132*7463f5adSRaviteja Laggyshetty #define SLAVE_MNOC_SF_MEM_NOC 13 133*7463f5adSRaviteja Laggyshetty #define SLAVE_SERVICE_MNOC 14 134*7463f5adSRaviteja Laggyshetty 135*7463f5adSRaviteja Laggyshetty #define MASTER_CDSP_PROC 0 136*7463f5adSRaviteja Laggyshetty #define SLAVE_CDSP_MEM_NOC 1 137*7463f5adSRaviteja Laggyshetty 138*7463f5adSRaviteja Laggyshetty #define MASTER_PCIE_ANOC_CFG 0 139*7463f5adSRaviteja Laggyshetty #define MASTER_PCIE_0 1 140*7463f5adSRaviteja Laggyshetty #define SLAVE_ANOC_PCIE_GEM_NOC 2 141*7463f5adSRaviteja Laggyshetty #define SLAVE_SERVICE_PCIE_ANOC 3 142*7463f5adSRaviteja Laggyshetty 143*7463f5adSRaviteja Laggyshetty #define MASTER_A1NOC_SNOC 0 144*7463f5adSRaviteja Laggyshetty #define MASTER_A2NOC_SNOC 1 145*7463f5adSRaviteja Laggyshetty #define MASTER_APSS_NOC 2 146*7463f5adSRaviteja Laggyshetty #define MASTER_CNOC_SNOC 3 147*7463f5adSRaviteja Laggyshetty #define SLAVE_SNOC_GEM_NOC_SF 4 148*7463f5adSRaviteja Laggyshetty 149*7463f5adSRaviteja Laggyshetty #endif 150