1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H 8 9 #define MASTER_CRYPTO 0 10 #define MASTER_SOCCP_PROC 1 11 #define MASTER_QDSS_ETR 2 12 #define MASTER_QDSS_ETR_1 3 13 #define SLAVE_A1NOC_SNOC 4 14 15 #define MASTER_UFS_MEM 0 16 #define MASTER_USB3_2 1 17 #define MASTER_USB4_2 2 18 #define SLAVE_A2NOC_SNOC 3 19 20 #define MASTER_QSPI_0 0 21 #define MASTER_QUP_0 1 22 #define MASTER_QUP_1 2 23 #define MASTER_QUP_2 3 24 #define MASTER_SP 4 25 #define MASTER_SDCC_2 5 26 #define MASTER_SDCC_4 6 27 #define MASTER_USB2 7 28 #define MASTER_USB3_MP 8 29 #define SLAVE_A3NOC_SNOC 9 30 31 #define MASTER_USB3_0 0 32 #define MASTER_USB3_1 1 33 #define MASTER_USB4_0 2 34 #define MASTER_USB4_1 3 35 #define SLAVE_A4NOC_HSCNOC 4 36 37 #define MASTER_QUP_CORE_0 0 38 #define MASTER_QUP_CORE_1 1 39 #define MASTER_QUP_CORE_2 2 40 #define SLAVE_QUP_CORE_0 3 41 #define SLAVE_QUP_CORE_1 4 42 #define SLAVE_QUP_CORE_2 5 43 44 #define MASTER_CNOC_CFG 0 45 #define SLAVE_AHB2PHY_SOUTH 1 46 #define SLAVE_AHB2PHY_NORTH 2 47 #define SLAVE_AHB2PHY_2 3 48 #define SLAVE_AHB2PHY_3 4 49 #define SLAVE_AV1_ENC_CFG 5 50 #define SLAVE_CAMERA_CFG 6 51 #define SLAVE_CLK_CTL 7 52 #define SLAVE_CRYPTO_0_CFG 8 53 #define SLAVE_DISPLAY_CFG 9 54 #define SLAVE_GFX3D_CFG 10 55 #define SLAVE_IMEM_CFG 11 56 #define SLAVE_PCIE_0_CFG 12 57 #define SLAVE_PCIE_1_CFG 13 58 #define SLAVE_PCIE_2_CFG 14 59 #define SLAVE_PCIE_3A_CFG 15 60 #define SLAVE_PCIE_3B_CFG 16 61 #define SLAVE_PCIE_4_CFG 17 62 #define SLAVE_PCIE_5_CFG 18 63 #define SLAVE_PCIE_6_CFG 19 64 #define SLAVE_PCIE_RSCC 20 65 #define SLAVE_PDM 21 66 #define SLAVE_PRNG 22 67 #define SLAVE_QDSS_CFG 23 68 #define SLAVE_QSPI_0 24 69 #define SLAVE_QUP_0 25 70 #define SLAVE_QUP_1 26 71 #define SLAVE_QUP_2 27 72 #define SLAVE_SDCC_2 28 73 #define SLAVE_SDCC_4 29 74 #define SLAVE_SMMUV3_CFG 30 75 #define SLAVE_TCSR 31 76 #define SLAVE_TLMM 32 77 #define SLAVE_UFS_MEM_CFG 33 78 #define SLAVE_USB2 34 79 #define SLAVE_USB3_0 35 80 #define SLAVE_USB3_1 36 81 #define SLAVE_USB3_2 37 82 #define SLAVE_USB3_MP 38 83 #define SLAVE_USB4_0 39 84 #define SLAVE_USB4_1 40 85 #define SLAVE_USB4_2 41 86 #define SLAVE_VENUS_CFG 42 87 #define SLAVE_CNOC_PCIE_SLAVE_EAST_CFG 43 88 #define SLAVE_CNOC_PCIE_SLAVE_WEST_CFG 44 89 #define SLAVE_LPASS_QTB_CFG 45 90 #define SLAVE_CNOC_MNOC_CFG 46 91 #define SLAVE_NSP_QTB_CFG 47 92 #define SLAVE_PCIE_EAST_ANOC_CFG 48 93 #define SLAVE_PCIE_WEST_ANOC_CFG 49 94 #define SLAVE_QDSS_STM 50 95 #define SLAVE_TCU 51 96 97 #define MASTER_HSCNOC_CNOC 0 98 #define SLAVE_AOSS 1 99 #define SLAVE_IPC_ROUTER_CFG 2 100 #define SLAVE_SOCCP 3 101 #define SLAVE_TME_CFG 4 102 #define SLAVE_APPSS 5 103 #define SLAVE_CNOC_CFG 6 104 #define SLAVE_BOOT_IMEM 7 105 #define SLAVE_IMEM 8 106 107 #define MASTER_GPU_TCU 0 108 #define MASTER_PCIE_TCU 1 109 #define MASTER_SYS_TCU 2 110 #define MASTER_APPSS_PROC 3 111 #define MASTER_AGGRE_NOC_EAST 4 112 #define MASTER_GFX3D 5 113 #define MASTER_LPASS_GEM_NOC 6 114 #define MASTER_MNOC_HF_MEM_NOC 7 115 #define MASTER_MNOC_SF_MEM_NOC 8 116 #define MASTER_COMPUTE_NOC 9 117 #define MASTER_PCIE_EAST 10 118 #define MASTER_PCIE_WEST 11 119 #define MASTER_SNOC_SF_MEM_NOC 12 120 #define MASTER_WLAN_Q6 13 121 #define MASTER_GIC 14 122 #define SLAVE_HSCNOC_CNOC 15 123 #define SLAVE_LLCC 16 124 #define SLAVE_PCIE_EAST 17 125 #define SLAVE_PCIE_WEST 18 126 127 #define MASTER_LPIAON_NOC 0 128 #define SLAVE_LPASS_GEM_NOC 1 129 130 #define MASTER_LPASS_LPINOC 0 131 #define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 132 133 #define MASTER_LPASS_PROC 0 134 #define SLAVE_LPICX_NOC_LPIAON_NOC 1 135 136 #define MASTER_LLCC 0 137 #define SLAVE_EBI1 1 138 139 #define MASTER_AV1_ENC 0 140 #define MASTER_CAMNOC_HF 1 141 #define MASTER_CAMNOC_ICP 2 142 #define MASTER_CAMNOC_SF 3 143 #define MASTER_EVA 4 144 #define MASTER_MDP 5 145 #define MASTER_CDSP_HCP 6 146 #define MASTER_VIDEO 7 147 #define MASTER_VIDEO_CV_PROC 8 148 #define MASTER_VIDEO_V_PROC 9 149 #define MASTER_CNOC_MNOC_CFG 10 150 #define SLAVE_MNOC_HF_MEM_NOC 11 151 #define SLAVE_MNOC_SF_MEM_NOC 12 152 #define SLAVE_SERVICE_MNOC 13 153 154 #define MASTER_CPUCP 0 155 #define SLAVE_NSINOC_SYSTEM_NOC 1 156 #define SLAVE_SERVICE_NSINOC 2 157 158 #define MASTER_CDSP_PROC 0 159 #define SLAVE_NSP0_HSC_NOC 1 160 161 #define MASTER_OOBMSS_SP_PROC 0 162 #define SLAVE_OOBMSS_SNOC 1 163 164 #define MASTER_PCIE_EAST_ANOC_CFG 0 165 #define MASTER_PCIE_0 1 166 #define MASTER_PCIE_1 2 167 #define MASTER_PCIE_5 3 168 #define SLAVE_PCIE_EAST_MEM_NOC 4 169 #define SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC 5 170 171 #define MASTER_HSCNOC_PCIE_EAST 0 172 #define MASTER_CNOC_PCIE_EAST_SLAVE_CFG 1 173 #define SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG 2 174 #define SLAVE_SERVICE_PCIE_EAST 3 175 #define SLAVE_PCIE_0 4 176 #define SLAVE_PCIE_1 5 177 #define SLAVE_PCIE_5 6 178 179 #define MASTER_PCIE_WEST_ANOC_CFG 0 180 #define MASTER_PCIE_2 1 181 #define MASTER_PCIE_3A 2 182 #define MASTER_PCIE_3B 3 183 #define MASTER_PCIE_4 4 184 #define MASTER_PCIE_6 5 185 #define SLAVE_PCIE_WEST_MEM_NOC 6 186 #define SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC 7 187 188 #define MASTER_HSCNOC_PCIE_WEST 0 189 #define MASTER_CNOC_PCIE_WEST_SLAVE_CFG 1 190 #define SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG 2 191 #define SLAVE_SERVICE_PCIE_WEST 3 192 #define SLAVE_PCIE_2 4 193 #define SLAVE_PCIE_3A 5 194 #define SLAVE_PCIE_3B 6 195 #define SLAVE_PCIE_4 7 196 #define SLAVE_PCIE_6 8 197 198 #define MASTER_A1NOC_SNOC 0 199 #define MASTER_A2NOC_SNOC 1 200 #define MASTER_A3NOC_SNOC 2 201 #define MASTER_NSINOC_SNOC 3 202 #define MASTER_OOBMSS 4 203 #define SLAVE_SNOC_GEM_NOC_SF 5 204 205 #endif 206