xref: /linux/include/dt-bindings/interconnect/qcom,sm8450.h (revision 0ae8c6252888d487f69b406369c3176172bb2064)
1*0ae8c625SVinod Koul /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*0ae8c625SVinod Koul /*
3*0ae8c625SVinod Koul  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4*0ae8c625SVinod Koul  * Copyright (c) 2021, Linaro Limited
5*0ae8c625SVinod Koul  */
6*0ae8c625SVinod Koul 
7*0ae8c625SVinod Koul #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8450_H
8*0ae8c625SVinod Koul #define __DT_BINDINGS_INTERCONNECT_QCOM_SM8450_H
9*0ae8c625SVinod Koul 
10*0ae8c625SVinod Koul #define MASTER_QSPI_0				0
11*0ae8c625SVinod Koul #define MASTER_QUP_1				1
12*0ae8c625SVinod Koul #define MASTER_A1NOC_CFG			2
13*0ae8c625SVinod Koul #define MASTER_SDCC_4				3
14*0ae8c625SVinod Koul #define MASTER_UFS_MEM				4
15*0ae8c625SVinod Koul #define MASTER_USB3_0				5
16*0ae8c625SVinod Koul #define SLAVE_A1NOC_SNOC			6
17*0ae8c625SVinod Koul #define SLAVE_SERVICE_A1NOC			7
18*0ae8c625SVinod Koul 
19*0ae8c625SVinod Koul #define	MASTER_QDSS_BAM				0
20*0ae8c625SVinod Koul #define	MASTER_QUP_0				1
21*0ae8c625SVinod Koul #define	MASTER_QUP_2				2
22*0ae8c625SVinod Koul #define	MASTER_A2NOC_CFG			3
23*0ae8c625SVinod Koul #define	MASTER_CRYPTO				4
24*0ae8c625SVinod Koul #define	MASTER_IPA				5
25*0ae8c625SVinod Koul #define	MASTER_SENSORS_PROC			6
26*0ae8c625SVinod Koul #define	MASTER_SP				7
27*0ae8c625SVinod Koul #define	MASTER_QDSS_ETR				8
28*0ae8c625SVinod Koul #define	MASTER_QDSS_ETR_1			9
29*0ae8c625SVinod Koul #define	MASTER_SDCC_2				10
30*0ae8c625SVinod Koul #define	SLAVE_A2NOC_SNOC			11
31*0ae8c625SVinod Koul #define	SLAVE_SERVICE_A2NOC			12
32*0ae8c625SVinod Koul 
33*0ae8c625SVinod Koul #define MASTER_QUP_CORE_0			0
34*0ae8c625SVinod Koul #define MASTER_QUP_CORE_1			1
35*0ae8c625SVinod Koul #define MASTER_QUP_CORE_2			2
36*0ae8c625SVinod Koul #define SLAVE_QUP_CORE_0			3
37*0ae8c625SVinod Koul #define SLAVE_QUP_CORE_1			4
38*0ae8c625SVinod Koul #define SLAVE_QUP_CORE_2			5
39*0ae8c625SVinod Koul 
40*0ae8c625SVinod Koul #define	MASTER_GEM_NOC_CNOC			0
41*0ae8c625SVinod Koul #define	MASTER_GEM_NOC_PCIE_SNOC		1
42*0ae8c625SVinod Koul #define	SLAVE_AHB2PHY_SOUTH			2
43*0ae8c625SVinod Koul #define	SLAVE_AHB2PHY_NORTH			3
44*0ae8c625SVinod Koul #define	SLAVE_AOSS			        4
45*0ae8c625SVinod Koul #define	SLAVE_CAMERA_CFG			5
46*0ae8c625SVinod Koul #define	SLAVE_CLK_CTL			        6
47*0ae8c625SVinod Koul #define	SLAVE_CDSP_CFG			        7
48*0ae8c625SVinod Koul #define	SLAVE_RBCPR_CX_CFG			8
49*0ae8c625SVinod Koul #define	SLAVE_RBCPR_MMCX_CFG			9
50*0ae8c625SVinod Koul #define	SLAVE_RBCPR_MXA_CFG			10
51*0ae8c625SVinod Koul #define	SLAVE_RBCPR_MXC_CFG			11
52*0ae8c625SVinod Koul #define	SLAVE_CRYPTO_0_CFG			12
53*0ae8c625SVinod Koul #define	SLAVE_CX_RDPM				13
54*0ae8c625SVinod Koul #define	SLAVE_DISPLAY_CFG			14
55*0ae8c625SVinod Koul #define	SLAVE_GFX3D_CFG			        15
56*0ae8c625SVinod Koul #define	SLAVE_IMEM_CFG			        16
57*0ae8c625SVinod Koul #define	SLAVE_IPA_CFG			        17
58*0ae8c625SVinod Koul #define	SLAVE_IPC_ROUTER_CFG			18
59*0ae8c625SVinod Koul #define	SLAVE_LPASS			        19
60*0ae8c625SVinod Koul #define	SLAVE_CNOC_MSS			        20
61*0ae8c625SVinod Koul #define	SLAVE_MX_RDPM				21
62*0ae8c625SVinod Koul #define	SLAVE_PCIE_0_CFG			22
63*0ae8c625SVinod Koul #define	SLAVE_PCIE_1_CFG			23
64*0ae8c625SVinod Koul #define	SLAVE_PDM				24
65*0ae8c625SVinod Koul #define	SLAVE_PIMEM_CFG				25
66*0ae8c625SVinod Koul #define	SLAVE_PRNG				26
67*0ae8c625SVinod Koul #define	SLAVE_QDSS_CFG				27
68*0ae8c625SVinod Koul #define	SLAVE_QSPI_0				28
69*0ae8c625SVinod Koul #define	SLAVE_QUP_0				29
70*0ae8c625SVinod Koul #define	SLAVE_QUP_1				30
71*0ae8c625SVinod Koul #define	SLAVE_QUP_2				31
72*0ae8c625SVinod Koul #define	SLAVE_SDCC_2				32
73*0ae8c625SVinod Koul #define	SLAVE_SDCC_4				33
74*0ae8c625SVinod Koul #define	SLAVE_SPSS_CFG				34
75*0ae8c625SVinod Koul #define	SLAVE_TCSR				35
76*0ae8c625SVinod Koul #define	SLAVE_TLMM				36
77*0ae8c625SVinod Koul #define	SLAVE_TME_CFG				37
78*0ae8c625SVinod Koul #define	SLAVE_UFS_MEM_CFG			38
79*0ae8c625SVinod Koul #define	SLAVE_USB3_0				39
80*0ae8c625SVinod Koul #define	SLAVE_VENUS_CFG				40
81*0ae8c625SVinod Koul #define	SLAVE_VSENSE_CTRL_CFG			41
82*0ae8c625SVinod Koul #define	SLAVE_A1NOC_CFG				42
83*0ae8c625SVinod Koul #define	SLAVE_A2NOC_CFG				43
84*0ae8c625SVinod Koul #define	SLAVE_DDRSS_CFG				44
85*0ae8c625SVinod Koul #define	SLAVE_CNOC_MNOC_CFG			45
86*0ae8c625SVinod Koul #define	SLAVE_PCIE_ANOC_CFG			46
87*0ae8c625SVinod Koul #define	SLAVE_SNOC_CFG				47
88*0ae8c625SVinod Koul #define	SLAVE_IMEM				48
89*0ae8c625SVinod Koul #define	SLAVE_PIMEM				49
90*0ae8c625SVinod Koul #define	SLAVE_SERVICE_CNOC			50
91*0ae8c625SVinod Koul #define	SLAVE_PCIE_0				51
92*0ae8c625SVinod Koul #define	SLAVE_PCIE_1				52
93*0ae8c625SVinod Koul #define	SLAVE_QDSS_STM				53
94*0ae8c625SVinod Koul #define	SLAVE_TCU				54
95*0ae8c625SVinod Koul 
96*0ae8c625SVinod Koul #define MASTER_GPU_TCU				0
97*0ae8c625SVinod Koul #define MASTER_SYS_TCU				1
98*0ae8c625SVinod Koul #define MASTER_APPSS_PROC			2
99*0ae8c625SVinod Koul #define MASTER_GFX3D				3
100*0ae8c625SVinod Koul #define MASTER_MSS_PROC				4
101*0ae8c625SVinod Koul #define MASTER_MNOC_HF_MEM_NOC			5
102*0ae8c625SVinod Koul #define MASTER_MNOC_SF_MEM_NOC			6
103*0ae8c625SVinod Koul #define MASTER_COMPUTE_NOC			7
104*0ae8c625SVinod Koul #define MASTER_ANOC_PCIE_GEM_NOC		8
105*0ae8c625SVinod Koul #define MASTER_SNOC_GC_MEM_NOC			9
106*0ae8c625SVinod Koul #define MASTER_SNOC_SF_MEM_NOC			10
107*0ae8c625SVinod Koul #define SLAVE_GEM_NOC_CNOC			11
108*0ae8c625SVinod Koul #define SLAVE_LLCC				12
109*0ae8c625SVinod Koul #define SLAVE_MEM_NOC_PCIE_SNOC			13
110*0ae8c625SVinod Koul #define MASTER_MNOC_HF_MEM_NOC_DISP		14
111*0ae8c625SVinod Koul #define MASTER_MNOC_SF_MEM_NOC_DISP		15
112*0ae8c625SVinod Koul #define MASTER_ANOC_PCIE_GEM_NOC_DISP		16
113*0ae8c625SVinod Koul #define SLAVE_LLCC_DISP				17
114*0ae8c625SVinod Koul 
115*0ae8c625SVinod Koul #define MASTER_CNOC_LPASS_AG_NOC		0
116*0ae8c625SVinod Koul #define MASTER_LPASS_PROC			1
117*0ae8c625SVinod Koul #define SLAVE_LPASS_CORE_CFG			2
118*0ae8c625SVinod Koul #define SLAVE_LPASS_LPI_CFG			3
119*0ae8c625SVinod Koul #define SLAVE_LPASS_MPU_CFG			4
120*0ae8c625SVinod Koul #define SLAVE_LPASS_TOP_CFG			5
121*0ae8c625SVinod Koul #define SLAVE_LPASS_SNOC			6
122*0ae8c625SVinod Koul #define SLAVE_SERVICES_LPASS_AML_NOC		7
123*0ae8c625SVinod Koul #define SLAVE_SERVICE_LPASS_AG_NOC		8
124*0ae8c625SVinod Koul 
125*0ae8c625SVinod Koul #define MASTER_LLCC				0
126*0ae8c625SVinod Koul #define SLAVE_EBI1				1
127*0ae8c625SVinod Koul #define MASTER_LLCC_DISP			2
128*0ae8c625SVinod Koul #define SLAVE_EBI1_DISP				3
129*0ae8c625SVinod Koul 
130*0ae8c625SVinod Koul #define MASTER_CAMNOC_HF			0
131*0ae8c625SVinod Koul #define MASTER_CAMNOC_ICP			1
132*0ae8c625SVinod Koul #define MASTER_CAMNOC_SF			2
133*0ae8c625SVinod Koul #define MASTER_MDP				3
134*0ae8c625SVinod Koul #define MASTER_CNOC_MNOC_CFG			4
135*0ae8c625SVinod Koul #define MASTER_ROTATOR				5
136*0ae8c625SVinod Koul #define MASTER_CDSP_HCP				6
137*0ae8c625SVinod Koul #define MASTER_VIDEO				7
138*0ae8c625SVinod Koul #define MASTER_VIDEO_CV_PROC			8
139*0ae8c625SVinod Koul #define MASTER_VIDEO_PROC			9
140*0ae8c625SVinod Koul #define MASTER_VIDEO_V_PROC			10
141*0ae8c625SVinod Koul #define SLAVE_MNOC_HF_MEM_NOC			11
142*0ae8c625SVinod Koul #define SLAVE_MNOC_SF_MEM_NOC			12
143*0ae8c625SVinod Koul #define SLAVE_SERVICE_MNOC			13
144*0ae8c625SVinod Koul #define MASTER_MDP_DISP				14
145*0ae8c625SVinod Koul #define MASTER_ROTATOR_DISP			15
146*0ae8c625SVinod Koul #define SLAVE_MNOC_HF_MEM_NOC_DISP		16
147*0ae8c625SVinod Koul #define SLAVE_MNOC_SF_MEM_NOC_DISP		17
148*0ae8c625SVinod Koul 
149*0ae8c625SVinod Koul #define MASTER_CDSP_NOC_CFG			0
150*0ae8c625SVinod Koul #define MASTER_CDSP_PROC			1
151*0ae8c625SVinod Koul #define SLAVE_CDSP_MEM_NOC			2
152*0ae8c625SVinod Koul #define SLAVE_SERVICE_NSP_NOC			3
153*0ae8c625SVinod Koul 
154*0ae8c625SVinod Koul #define MASTER_PCIE_ANOC_CFG			0
155*0ae8c625SVinod Koul #define MASTER_PCIE_0				1
156*0ae8c625SVinod Koul #define MASTER_PCIE_1				2
157*0ae8c625SVinod Koul #define SLAVE_ANOC_PCIE_GEM_NOC			3
158*0ae8c625SVinod Koul #define SLAVE_SERVICE_PCIE_ANOC			4
159*0ae8c625SVinod Koul 
160*0ae8c625SVinod Koul #define MASTER_GIC_AHB				0
161*0ae8c625SVinod Koul #define MASTER_A1NOC_SNOC			1
162*0ae8c625SVinod Koul #define MASTER_A2NOC_SNOC			2
163*0ae8c625SVinod Koul #define MASTER_LPASS_ANOC			3
164*0ae8c625SVinod Koul #define MASTER_SNOC_CFG				4
165*0ae8c625SVinod Koul #define MASTER_PIMEM				5
166*0ae8c625SVinod Koul #define MASTER_GIC				6
167*0ae8c625SVinod Koul #define SLAVE_SNOC_GEM_NOC_GC			7
168*0ae8c625SVinod Koul #define SLAVE_SNOC_GEM_NOC_SF			8
169*0ae8c625SVinod Koul #define SLAVE_SERVICE_SNOC			9
170*0ae8c625SVinod Koul 
171*0ae8c625SVinod Koul #endif
172