1*4b54bf47SLeonard Crestez /* SPDX-License-Identifier: GPL-2.0 */ 2*4b54bf47SLeonard Crestez /* 3*4b54bf47SLeonard Crestez * Interconnect framework driver for i.MX SoC 4*4b54bf47SLeonard Crestez * 5*4b54bf47SLeonard Crestez * Copyright (c) 2019-2020, NXP 6*4b54bf47SLeonard Crestez */ 7*4b54bf47SLeonard Crestez 8*4b54bf47SLeonard Crestez #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H 9*4b54bf47SLeonard Crestez #define __DT_BINDINGS_INTERCONNECT_IMX8MN_H 10*4b54bf47SLeonard Crestez 11*4b54bf47SLeonard Crestez #define IMX8MN_ICN_NOC 1 12*4b54bf47SLeonard Crestez #define IMX8MN_ICS_DRAM 2 13*4b54bf47SLeonard Crestez #define IMX8MN_ICS_OCRAM 3 14*4b54bf47SLeonard Crestez #define IMX8MN_ICM_A53 4 15*4b54bf47SLeonard Crestez 16*4b54bf47SLeonard Crestez #define IMX8MN_ICM_GPU 5 17*4b54bf47SLeonard Crestez #define IMX8MN_ICN_GPU 6 18*4b54bf47SLeonard Crestez 19*4b54bf47SLeonard Crestez #define IMX8MN_ICM_CSI1 7 20*4b54bf47SLeonard Crestez #define IMX8MN_ICM_CSI2 8 21*4b54bf47SLeonard Crestez #define IMX8MN_ICM_ISI 9 22*4b54bf47SLeonard Crestez #define IMX8MN_ICM_LCDIF 10 23*4b54bf47SLeonard Crestez #define IMX8MN_ICN_MIPI 11 24*4b54bf47SLeonard Crestez 25*4b54bf47SLeonard Crestez #define IMX8MN_ICM_USB 12 26*4b54bf47SLeonard Crestez 27*4b54bf47SLeonard Crestez #define IMX8MN_ICM_SDMA2 13 28*4b54bf47SLeonard Crestez #define IMX8MN_ICM_SDMA3 14 29*4b54bf47SLeonard Crestez #define IMX8MN_ICN_AUDIO 15 30*4b54bf47SLeonard Crestez 31*4b54bf47SLeonard Crestez #define IMX8MN_ICN_ENET 16 32*4b54bf47SLeonard Crestez #define IMX8MN_ICM_ENET 17 33*4b54bf47SLeonard Crestez 34*4b54bf47SLeonard Crestez #define IMX8MN_ICM_NAND 18 35*4b54bf47SLeonard Crestez #define IMX8MN_ICM_SDMA1 19 36*4b54bf47SLeonard Crestez #define IMX8MN_ICM_USDHC1 20 37*4b54bf47SLeonard Crestez #define IMX8MN_ICM_USDHC2 21 38*4b54bf47SLeonard Crestez #define IMX8MN_ICM_USDHC3 22 39*4b54bf47SLeonard Crestez #define IMX8MN_ICN_MAIN 23 40*4b54bf47SLeonard Crestez 41*4b54bf47SLeonard Crestez #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ 42