1*18c74d56SLuca Weiss /* SPDX-License-Identifier: GPL-2.0-only */ 2*18c74d56SLuca Weiss /* 3*18c74d56SLuca Weiss * Copyright (c) 2020 The Linux Foundation. All rights reserved. 4*18c74d56SLuca Weiss */ 5*18c74d56SLuca Weiss 6*18c74d56SLuca Weiss #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H 7*18c74d56SLuca Weiss #define _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H 8*18c74d56SLuca Weiss 9*18c74d56SLuca Weiss #ifndef PM7325_SID 10*18c74d56SLuca Weiss #define PM7325_SID 1 11*18c74d56SLuca Weiss #endif 12*18c74d56SLuca Weiss 13*18c74d56SLuca Weiss #include <dt-bindings/iio/qcom,spmi-vadc.h> 14*18c74d56SLuca Weiss 15*18c74d56SLuca Weiss /* ADC channels for PM7325_ADC for PMIC7 */ 16*18c74d56SLuca Weiss #define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND) 17*18c74d56SLuca Weiss #define PM7325_ADC7_1P25VREF (PM7325_SID << 8 | ADC7_1P25VREF) 18*18c74d56SLuca Weiss #define PM7325_ADC7_VREF_VADC (PM7325_SID << 8 | ADC7_VREF_VADC) 19*18c74d56SLuca Weiss #define PM7325_ADC7_DIE_TEMP (PM7325_SID << 8 | ADC7_DIE_TEMP) 20*18c74d56SLuca Weiss 21*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM1 (PM7325_SID << 8 | ADC7_AMUX_THM1) 22*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM2 (PM7325_SID << 8 | ADC7_AMUX_THM2) 23*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM3 (PM7325_SID << 8 | ADC7_AMUX_THM3) 24*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM4 (PM7325_SID << 8 | ADC7_AMUX_THM4) 25*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM5 (PM7325_SID << 8 | ADC7_AMUX_THM5) 26*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO1 (PM7325_SID << 8 | ADC7_GPIO1) 27*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO2 (PM7325_SID << 8 | ADC7_GPIO2) 28*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO3 (PM7325_SID << 8 | ADC7_GPIO3) 29*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO4 (PM7325_SID << 8 | ADC7_GPIO4) 30*18c74d56SLuca Weiss 31*18c74d56SLuca Weiss /* 30k pull-up1 */ 32*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM1_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_30K_PU) 33*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM2_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_30K_PU) 34*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM3_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_30K_PU) 35*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM4_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_30K_PU) 36*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM5_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_30K_PU) 37*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO1_30K_PU (PM7325_SID << 8 | ADC7_GPIO1_30K_PU) 38*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO2_30K_PU (PM7325_SID << 8 | ADC7_GPIO2_30K_PU) 39*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO3_30K_PU (PM7325_SID << 8 | ADC7_GPIO3_30K_PU) 40*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO4_30K_PU (PM7325_SID << 8 | ADC7_GPIO4_30K_PU) 41*18c74d56SLuca Weiss 42*18c74d56SLuca Weiss /* 100k pull-up2 */ 43*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM1_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_100K_PU) 44*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM2_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_100K_PU) 45*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM3_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_100K_PU) 46*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM4_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_100K_PU) 47*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM5_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_100K_PU) 48*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO1_100K_PU (PM7325_SID << 8 | ADC7_GPIO1_100K_PU) 49*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO2_100K_PU (PM7325_SID << 8 | ADC7_GPIO2_100K_PU) 50*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO3_100K_PU (PM7325_SID << 8 | ADC7_GPIO3_100K_PU) 51*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO4_100K_PU (PM7325_SID << 8 | ADC7_GPIO4_100K_PU) 52*18c74d56SLuca Weiss 53*18c74d56SLuca Weiss /* 400k pull-up3 */ 54*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM1_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_400K_PU) 55*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM2_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_400K_PU) 56*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM3_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_400K_PU) 57*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM4_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_400K_PU) 58*18c74d56SLuca Weiss #define PM7325_ADC7_AMUX_THM5_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_400K_PU) 59*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO1_400K_PU (PM7325_SID << 8 | ADC7_GPIO1_400K_PU) 60*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO2_400K_PU (PM7325_SID << 8 | ADC7_GPIO2_400K_PU) 61*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO3_400K_PU (PM7325_SID << 8 | ADC7_GPIO3_400K_PU) 62*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO4_400K_PU (PM7325_SID << 8 | ADC7_GPIO4_400K_PU) 63*18c74d56SLuca Weiss 64*18c74d56SLuca Weiss /* 1/3 Divider */ 65*18c74d56SLuca Weiss #define PM7325_ADC7_GPIO4_DIV3 (PM7325_SID << 8 | ADC7_GPIO4_DIV3) 66*18c74d56SLuca Weiss 67*18c74d56SLuca Weiss #define PM7325_ADC7_VPH_PWR (PM7325_SID << 8 | ADC7_VPH_PWR) 68*18c74d56SLuca Weiss 69*18c74d56SLuca Weiss #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H */ 70