1*7f915eefSChiYuan Huang /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2*7f915eefSChiYuan Huang 3*7f915eefSChiYuan Huang #ifndef __DT_BINDINGS_MEDIATEK_MT6370_ADC_H__ 4*7f915eefSChiYuan Huang #define __DT_BINDINGS_MEDIATEK_MT6370_ADC_H__ 5*7f915eefSChiYuan Huang 6*7f915eefSChiYuan Huang /* ADC Channel Index */ 7*7f915eefSChiYuan Huang #define MT6370_CHAN_VBUSDIV5 0 8*7f915eefSChiYuan Huang #define MT6370_CHAN_VBUSDIV2 1 9*7f915eefSChiYuan Huang #define MT6370_CHAN_VSYS 2 10*7f915eefSChiYuan Huang #define MT6370_CHAN_VBAT 3 11*7f915eefSChiYuan Huang #define MT6370_CHAN_TS_BAT 4 12*7f915eefSChiYuan Huang #define MT6370_CHAN_IBUS 5 13*7f915eefSChiYuan Huang #define MT6370_CHAN_IBAT 6 14*7f915eefSChiYuan Huang #define MT6370_CHAN_CHG_VDDP 7 15*7f915eefSChiYuan Huang #define MT6370_CHAN_TEMP_JC 8 16*7f915eefSChiYuan Huang #define MT6370_CHAN_MAX 9 17*7f915eefSChiYuan Huang 18*7f915eefSChiYuan Huang #endif 19