1*9f01881bSAkhil R /* SPDX-License-Identifier: GPL-2.0 */ 2*9f01881bSAkhil R /* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */ 3*9f01881bSAkhil R 4*9f01881bSAkhil R /* 5*9f01881bSAkhil R * This header provides constants for the nvidia,tegra241-gpio DT binding. 6*9f01881bSAkhil R * 7*9f01881bSAkhil R * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8*9f01881bSAkhil R * provide names for this. 9*9f01881bSAkhil R * 10*9f01881bSAkhil R * The second cell contains standard flag values specified in gpio.h. 11*9f01881bSAkhil R */ 12*9f01881bSAkhil R 13*9f01881bSAkhil R #ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H 14*9f01881bSAkhil R #define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H 15*9f01881bSAkhil R 16*9f01881bSAkhil R #include <dt-bindings/gpio/gpio.h> 17*9f01881bSAkhil R 18*9f01881bSAkhil R /* GPIOs implemented by main GPIO controller */ 19*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_A 0 20*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_B 1 21*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_C 2 22*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_D 3 23*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_E 4 24*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_F 5 25*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_G 6 26*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_H 7 27*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_I 8 28*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_J 9 29*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_K 10 30*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO_PORT_L 11 31*9f01881bSAkhil R 32*9f01881bSAkhil R #define TEGRA241_MAIN_GPIO(port, offset) \ 33*9f01881bSAkhil R ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset)) 34*9f01881bSAkhil R 35*9f01881bSAkhil R /* GPIOs implemented by AON GPIO controller */ 36*9f01881bSAkhil R #define TEGRA241_AON_GPIO_PORT_AA 0 37*9f01881bSAkhil R #define TEGRA241_AON_GPIO_PORT_BB 1 38*9f01881bSAkhil R 39*9f01881bSAkhil R #define TEGRA241_AON_GPIO(port, offset) \ 40*9f01881bSAkhil R ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset)) 41*9f01881bSAkhil R 42*9f01881bSAkhil R #endif 43