xref: /linux/include/dt-bindings/gpio/tegra234-gpio.h (revision a8b10f3d12cfc168a389f3d97e1f762732d4d849)
1*a8b10f3dSPrathamesh Shete /* SPDX-License-Identifier: GPL-2.0 */
2*a8b10f3dSPrathamesh Shete /* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */
3*a8b10f3dSPrathamesh Shete 
4*a8b10f3dSPrathamesh Shete /*
5*a8b10f3dSPrathamesh Shete  * This header provides constants for binding nvidia,tegra234-gpio*.
6*a8b10f3dSPrathamesh Shete  *
7*a8b10f3dSPrathamesh Shete  * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
8*a8b10f3dSPrathamesh Shete  * provide names for this.
9*a8b10f3dSPrathamesh Shete  *
10*a8b10f3dSPrathamesh Shete  * The second cell contains standard flag values specified in gpio.h.
11*a8b10f3dSPrathamesh Shete  */
12*a8b10f3dSPrathamesh Shete 
13*a8b10f3dSPrathamesh Shete #ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
14*a8b10f3dSPrathamesh Shete #define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
15*a8b10f3dSPrathamesh Shete 
16*a8b10f3dSPrathamesh Shete #include <dt-bindings/gpio/gpio.h>
17*a8b10f3dSPrathamesh Shete 
18*a8b10f3dSPrathamesh Shete /* GPIOs implemented by main GPIO controller */
19*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_A   0
20*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_B   1
21*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_C   2
22*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_D   3
23*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_E   4
24*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_F   5
25*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_G   6
26*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_H   7
27*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_I   8
28*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_J   9
29*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_K  10
30*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_L  11
31*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_M  12
32*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_N  13
33*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_P  14
34*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_Q  15
35*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_R  16
36*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_S  17
37*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_T  18
38*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_U  19
39*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_V  20
40*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_X  21
41*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_Y  22
42*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_Z  23
43*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AC 24
44*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AD 25
45*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AE 26
46*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AF 27
47*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AG 28
48*a8b10f3dSPrathamesh Shete 
49*a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO(port, offset) \
50*a8b10f3dSPrathamesh Shete 	((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
51*a8b10f3dSPrathamesh Shete 
52*a8b10f3dSPrathamesh Shete /* GPIOs implemented by AON GPIO controller */
53*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_AA 0
54*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_BB 1
55*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_CC 2
56*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_DD 3
57*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_EE 4
58*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_GG 5
59*a8b10f3dSPrathamesh Shete 
60*a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO(port, offset) \
61*a8b10f3dSPrathamesh Shete 	((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
62*a8b10f3dSPrathamesh Shete 
63*a8b10f3dSPrathamesh Shete #endif
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