1a8b10f3dSPrathamesh Shete /* SPDX-License-Identifier: GPL-2.0 */ 2a8b10f3dSPrathamesh Shete /* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ 3a8b10f3dSPrathamesh Shete 4a8b10f3dSPrathamesh Shete /* 5a8b10f3dSPrathamesh Shete * This header provides constants for binding nvidia,tegra234-gpio*. 6a8b10f3dSPrathamesh Shete * 7a8b10f3dSPrathamesh Shete * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8a8b10f3dSPrathamesh Shete * provide names for this. 9a8b10f3dSPrathamesh Shete * 10a8b10f3dSPrathamesh Shete * The second cell contains standard flag values specified in gpio.h. 11a8b10f3dSPrathamesh Shete */ 12a8b10f3dSPrathamesh Shete 13a8b10f3dSPrathamesh Shete #ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 14a8b10f3dSPrathamesh Shete #define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 15a8b10f3dSPrathamesh Shete 16a8b10f3dSPrathamesh Shete #include <dt-bindings/gpio/gpio.h> 17a8b10f3dSPrathamesh Shete 18a8b10f3dSPrathamesh Shete /* GPIOs implemented by main GPIO controller */ 19a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_A 0 20a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_B 1 21a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_C 2 22a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_D 3 23a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_E 4 24a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_F 5 25a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_G 6 26a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_H 7 27a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_I 8 28a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_J 9 29a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_K 10 30a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_L 11 31a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_M 12 32a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_N 13 33a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_P 14 34a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_Q 15 35a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_R 16 36*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_X 17 37*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_Y 18 38*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_Z 19 39*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AC 20 40*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AD 21 41*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AE 22 42*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AF 23 43*12382ad0SPrathamesh Shete #define TEGRA234_MAIN_GPIO_PORT_AG 24 44a8b10f3dSPrathamesh Shete 45a8b10f3dSPrathamesh Shete #define TEGRA234_MAIN_GPIO(port, offset) \ 46a8b10f3dSPrathamesh Shete ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) 47a8b10f3dSPrathamesh Shete 48a8b10f3dSPrathamesh Shete /* GPIOs implemented by AON GPIO controller */ 49a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_AA 0 50a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_BB 1 51a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_CC 2 52a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_DD 3 53a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_EE 4 54a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO_PORT_GG 5 55a8b10f3dSPrathamesh Shete 56a8b10f3dSPrathamesh Shete #define TEGRA234_AON_GPIO(port, offset) \ 57a8b10f3dSPrathamesh Shete ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) 58a8b10f3dSPrathamesh Shete 59a8b10f3dSPrathamesh Shete #endif 60