1*4002ccd2SPrathamesh Shete /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2*4002ccd2SPrathamesh Shete /* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ 3*4002ccd2SPrathamesh Shete 4*4002ccd2SPrathamesh Shete /* 5*4002ccd2SPrathamesh Shete * This header provides constants for binding nvidia,tegra238-gpio*. 6*4002ccd2SPrathamesh Shete * 7*4002ccd2SPrathamesh Shete * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8*4002ccd2SPrathamesh Shete * provide names for this. 9*4002ccd2SPrathamesh Shete * 10*4002ccd2SPrathamesh Shete * The second cell contains standard flag values specified in gpio.h. 11*4002ccd2SPrathamesh Shete */ 12*4002ccd2SPrathamesh Shete 13*4002ccd2SPrathamesh Shete #ifndef _DT_BINDINGS_GPIO_TEGRA238_GPIO_H 14*4002ccd2SPrathamesh Shete #define _DT_BINDINGS_GPIO_TEGRA238_GPIO_H 15*4002ccd2SPrathamesh Shete 16*4002ccd2SPrathamesh Shete #include <dt-bindings/gpio/gpio.h> 17*4002ccd2SPrathamesh Shete 18*4002ccd2SPrathamesh Shete /* GPIOs implemented by main GPIO controller */ 19*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_A 0 20*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_B 1 21*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_C 2 22*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_D 3 23*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_E 4 24*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_F 5 25*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_G 6 26*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_H 7 27*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_J 8 28*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_K 9 29*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_L 10 30*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_M 11 31*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_N 12 32*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_P 13 33*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_Q 14 34*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_R 15 35*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_S 16 36*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_T 17 37*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_U 18 38*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_V 19 39*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_W 20 40*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO_PORT_X 21 41*4002ccd2SPrathamesh Shete 42*4002ccd2SPrathamesh Shete #define TEGRA238_MAIN_GPIO(port, offset) \ 43*4002ccd2SPrathamesh Shete ((TEGRA238_MAIN_GPIO_PORT_##port * 8) + (offset)) 44*4002ccd2SPrathamesh Shete 45*4002ccd2SPrathamesh Shete /* GPIOs implemented by AON GPIO controller */ 46*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_AA 0 47*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_BB 1 48*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_CC 2 49*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_DD 3 50*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_EE 4 51*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_FF 5 52*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_GG 6 53*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO_PORT_HH 7 54*4002ccd2SPrathamesh Shete 55*4002ccd2SPrathamesh Shete #define TEGRA238_AON_GPIO(port, offset) \ 56*4002ccd2SPrathamesh Shete ((TEGRA238_AON_GPIO_PORT_##port * 8) + (offset)) 57*4002ccd2SPrathamesh Shete 58*4002ccd2SPrathamesh Shete #endif 59