xref: /linux/include/dt-bindings/gce/mt8192-gce.h (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2020 MediaTek Inc.
4  * Author: Yongqiang Niu <yongqiang.niu@mediatek.com>
5  */
6 
7 #ifndef _DT_BINDINGS_GCE_MT8192_H
8 #define _DT_BINDINGS_GCE_MT8192_H
9 
10 /* assign timeout 0 also means default */
11 #define CMDQ_NO_TIMEOUT		0xffffffff
12 #define CMDQ_TIMEOUT_DEFAULT	1000
13 
14 /* GCE thread priority */
15 #define CMDQ_THR_PRIO_LOWEST	0
16 #define CMDQ_THR_PRIO_1		1
17 #define CMDQ_THR_PRIO_2		2
18 #define CMDQ_THR_PRIO_3		3
19 #define CMDQ_THR_PRIO_4		4
20 #define CMDQ_THR_PRIO_5		5
21 #define CMDQ_THR_PRIO_6		6
22 #define CMDQ_THR_PRIO_HIGHEST	7
23 
24 /* CPR count in 32bit register */
25 #define GCE_CPR_COUNT		1312
26 
27 /* GCE subsys table */
28 #define SUBSYS_1300XXXX		0
29 #define SUBSYS_1400XXXX		1
30 #define SUBSYS_1401XXXX		2
31 #define SUBSYS_1402XXXX		3
32 #define SUBSYS_1502XXXX		4
33 #define SUBSYS_1880XXXX		5
34 #define SUBSYS_1881XXXX		6
35 #define SUBSYS_1882XXXX		7
36 #define SUBSYS_1883XXXX		8
37 #define SUBSYS_1884XXXX		9
38 #define SUBSYS_1000XXXX		10
39 #define SUBSYS_1001XXXX		11
40 #define SUBSYS_1002XXXX		12
41 #define SUBSYS_1003XXXX		13
42 #define SUBSYS_1004XXXX		14
43 #define SUBSYS_1005XXXX		15
44 #define SUBSYS_1020XXXX		16
45 #define SUBSYS_1028XXXX		17
46 #define SUBSYS_1700XXXX		18
47 #define SUBSYS_1701XXXX		19
48 #define SUBSYS_1702XXXX		20
49 #define SUBSYS_1703XXXX		21
50 #define SUBSYS_1800XXXX		22
51 #define SUBSYS_1801XXXX		23
52 #define SUBSYS_1802XXXX		24
53 #define SUBSYS_1804XXXX		25
54 #define SUBSYS_1805XXXX		26
55 #define SUBSYS_1808XXXX		27
56 #define SUBSYS_180aXXXX		28
57 #define SUBSYS_180bXXXX		29
58 
59 #define CMDQ_EVENT_VDEC_LAT_SOF_0			0
60 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0		1
61 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1		2
62 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2		3
63 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3		4
64 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4		5
65 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5		6
66 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6		7
67 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_0			8
68 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_1			9
69 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_2			10
70 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_3			11
71 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_4			12
72 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_5			13
73 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_6			14
74 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_7			15
75 
76 #define CMDQ_EVENT_ISP_FRAME_DONE_A			65
77 #define CMDQ_EVENT_ISP_FRAME_DONE_B			66
78 #define CMDQ_EVENT_ISP_FRAME_DONE_C			67
79 #define CMDQ_EVENT_CAMSV0_PASS1_DONE			68
80 #define CMDQ_EVENT_CAMSV02_PASS1_DONE			69
81 #define CMDQ_EVENT_CAMSV1_PASS1_DONE			70
82 #define CMDQ_EVENT_CAMSV2_PASS1_DONE			71
83 #define CMDQ_EVENT_CAMSV3_PASS1_DONE			72
84 #define CMDQ_EVENT_MRAW_0_PASS1_DONE			73
85 #define CMDQ_EVENT_MRAW_1_PASS1_DONE			74
86 #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL		75
87 #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL		76
88 #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL		77
89 #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL		78
90 #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL		79
91 #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL		80
92 #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL		81
93 #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL		82
94 #define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL		83
95 #define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL		84
96 #define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL		85
97 #define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL		86
98 #define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL		87
99 #define CMDQ_EVENT_TG_OVRUN_A_INT			88
100 #define CMDQ_EVENT_DMA_R1_ERROR_A_INT			89
101 #define CMDQ_EVENT_TG_OVRUN_B_INT			90
102 #define CMDQ_EVENT_DMA_R1_ERROR_B_INT			91
103 #define CMDQ_EVENT_TG_OVRUN_C_INT			92
104 #define CMDQ_EVENT_DMA_R1_ERROR_C_INT			93
105 #define CMDQ_EVENT_TG_OVRUN_M0_INT			94
106 #define CMDQ_EVENT_DMA_R1_ERROR_M0_INT			95
107 #define CMDQ_EVENT_TG_GRABERR_M0_INT			96
108 #define CMDQ_EVENT_TG_GRABERR_M1_INT			97
109 #define CMDQ_EVENT_TG_GRABERR_A_INT			98
110 #define CMDQ_EVENT_CQ_VR_SNAP_A_INT			99
111 #define CMDQ_EVENT_TG_GRABERR_B_INT			100
112 #define CMDQ_EVENT_CQ_VR_SNAP_B_INT			101
113 #define CMDQ_EVENT_TG_GRABERR_C_INT			102
114 #define CMDQ_EVENT_CQ_VR_SNAP_C_INT			103
115 
116 #define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE			129
117 #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE			130
118 #define CMDQ_EVENT_JPGENC_CMDQ_DONE			131
119 #define CMDQ_EVENT_VENC_CMDQ_MB_DONE			132
120 #define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE		133
121 #define CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_DONE	134
122 #define CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_DONE	135
123 #define CMDQ_EVENT_VENC_CMDQ_PPS_DONE			136
124 #define CMDQ_EVENT_VENC_CMDQ_SPS_DONE			137
125 #define CMDQ_EVENT_VENC_CMDQ_VPS_DONE			138
126 
127 #define CMDQ_EVENT_VDEC_CORE0_SOF_0			160
128 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0		161
129 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1		162
130 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2		163
131 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3		164
132 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4		165
133 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5		166
134 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6		167
135 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_0		168
136 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_1		169
137 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_2		170
138 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_3		171
139 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_4		172
140 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_5		173
141 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_6		174
142 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_7		175
143 #define CMDQ_EVENT_FDVT_DONE				177
144 #define CMDQ_EVENT_FE_DONE				178
145 #define CMDQ_EVENT_RSC_DONE				179
146 #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT			180
147 #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT			181
148 
149 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_0		193
150 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_1		194
151 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_2		195
152 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_3		196
153 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_4		197
154 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_5		198
155 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_6		199
156 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_7		200
157 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_8		201
158 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_9		202
159 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_10		203
160 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_11		204
161 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_12		205
162 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_13		206
163 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_14		207
164 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_15		208
165 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_16		209
166 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_17		210
167 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_18		211
168 #define CMDQ_EVENT_IMG2_DIP_DMA_ERR_EVENT		212
169 #define CMDQ_EVENT_IMG2_AMD_FRAME_DONE			213
170 #define CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC		214
171 #define CMDQ_EVENT_IMG2_WPE_A_DONE_LINK_MISC		215
172 #define CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC		216
173 
174 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0		225
175 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1		226
176 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2		227
177 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3		228
178 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4		229
179 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5		230
180 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6		231
181 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7		232
182 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8		233
183 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9		234
184 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10		235
185 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11		236
186 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12		237
187 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13		238
188 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14		239
189 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_15		240
190 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_16		241
191 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_17		242
192 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_18		243
193 #define CMDQ_EVENT_IMG1_DIP_DMA_ERR_EVENT		244
194 #define CMDQ_EVENT_IMG1_AMD_FRAME_DONE			245
195 #define CMDQ_EVENT_IMG1_MFB_DONE_LINK_MISC		246
196 #define CMDQ_EVENT_IMG1_WPE_A_DONE_LINK_MISC		247
197 #define CMDQ_EVENT_IMG1_MSS_DONE_LINK_MISC		248
198 
199 #define CMDQ_EVENT_MDP_RDMA0_SOF			256
200 #define CMDQ_EVENT_MDP_RDMA1_SOF			257
201 #define CMDQ_EVENT_MDP_AAL0_SOF				258
202 #define CMDQ_EVENT_MDP_AAL1_SOF				259
203 #define CMDQ_EVENT_MDP_HDR0_SOF				260
204 #define CMDQ_EVENT_MDP_HDR1_SOF				261
205 #define CMDQ_EVENT_MDP_RSZ0_SOF				262
206 #define CMDQ_EVENT_MDP_RSZ1_SOF				263
207 #define CMDQ_EVENT_MDP_WROT0_SOF			264
208 #define CMDQ_EVENT_MDP_WROT1_SOF			265
209 #define CMDQ_EVENT_MDP_TDSHP0_SOF			266
210 #define CMDQ_EVENT_MDP_TDSHP1_SOF			267
211 #define CMDQ_EVENT_IMG_DL_RELAY0_SOF			268
212 #define CMDQ_EVENT_IMG_DL_RELAY1_SOF			269
213 #define CMDQ_EVENT_MDP_COLOR0_SOF			270
214 #define CMDQ_EVENT_MDP_COLOR1_SOF			271
215 #define CMDQ_EVENT_MDP_WROT1_FRAME_DONE			290
216 #define CMDQ_EVENT_MDP_WROT0_FRAME_DONE			291
217 #define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE		294
218 #define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE		295
219 #define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE			302
220 #define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE			303
221 #define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE			306
222 #define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE			307
223 #define CMDQ_EVENT_MDP_HDR1_FRAME_DONE			308
224 #define CMDQ_EVENT_MDP_HDR0_FRAME_DONE			309
225 #define CMDQ_EVENT_MDP_COLOR1_FRAME_DONE		312
226 #define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE		313
227 #define CMDQ_EVENT_MDP_AAL1_FRAME_DONE			316
228 #define CMDQ_EVENT_MDP_AAL0_FRAME_DONE			317
229 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0		320
230 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1		321
231 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2		322
232 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3		323
233 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4		324
234 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5		325
235 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6		326
236 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7		327
237 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8		328
238 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9		329
239 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10		330
240 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11		331
241 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12		332
242 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13		333
243 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14		334
244 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15		335
245 #define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT	338
246 #define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT	339
247 #define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT	342
248 #define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT	343
249 
250 #define CMDQ_EVENT_DISP_OVL0_SOF			384
251 #define CMDQ_EVENT_DISP_OVL0_2L_SOF			385
252 #define CMDQ_EVENT_DISP_RDMA0_SOF			386
253 #define CMDQ_EVENT_DISP_RSZ0_SOF			387
254 #define CMDQ_EVENT_DISP_COLOR0_SOF			388
255 #define CMDQ_EVENT_DISP_CCORR0_SOF			389
256 #define CMDQ_EVENT_DISP_AAL0_SOF			390
257 #define CMDQ_EVENT_DISP_GAMMA0_SOF			391
258 #define CMDQ_EVENT_DISP_POSTMASK0_SOF			392
259 #define CMDQ_EVENT_DISP_DITHER0_SOF			393
260 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_SOF		394
261 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_SOF		395
262 #define CMDQ_EVENT_DSI0_SOF				396
263 #define CMDQ_EVENT_DISP_WDMA0_SOF			397
264 #define CMDQ_EVENT_DISP_UFBC_WDMA0_SOF			398
265 #define CMDQ_EVENT_DISP_PWM0_SOF			399
266 #define CMDQ_EVENT_DISP_OVL2_2L_SOF			400
267 #define CMDQ_EVENT_DISP_RDMA4_SOF			401
268 #define CMDQ_EVENT_DISP_DPI0_SOF			402
269 #define CMDQ_EVENT_MDP_RDMA4_SOF			403
270 #define CMDQ_EVENT_MDP_HDR4_SOF				404
271 #define CMDQ_EVENT_MDP_RSZ4_SOF				405
272 #define CMDQ_EVENT_MDP_AAL4_SOF				406
273 #define CMDQ_EVENT_MDP_TDSHP4_SOF			407
274 #define CMDQ_EVENT_MDP_COLOR4_SOF			408
275 #define CMDQ_EVENT_DISP_Y2R0_SOF			409
276 #define CMDQ_EVENT_MDP_TDSHP4_FRAME_DONE		410
277 #define CMDQ_EVENT_MDP_RSZ4_FRAME_DONE			411
278 #define CMDQ_EVENT_MDP_RDMA4_FRAME_DONE			412
279 #define CMDQ_EVENT_MDP_HDR4_FRAME_DONE			413
280 #define CMDQ_EVENT_MDP_COLOR4_FRAME_DONE		414
281 #define CMDQ_EVENT_MDP_AAL4_FRAME_DONE			415
282 #define CMDQ_EVENT_DSI0_FRAME_DONE			416
283 #define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE		417
284 #define CMDQ_EVENT_DISP_UFBC_WDMA0_FRAME_DONE		418
285 #define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE			419
286 #define CMDQ_EVENT_DISP_RDMA4_FRAME_DONE		420
287 #define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE		421
288 #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE		422
289 #define CMDQ_EVENT_DISP_OVL2_2L_FRAME_DONE		423
290 #define CMDQ_EVENT_DISP_OVL0_FRAME_DONE			424
291 #define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE		425
292 #define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE		426
293 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_FRAME_DONE	427
294 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE	428
295 #define CMDQ_EVENT_DISP_DPI0_FRAME_DONE			429
296 #define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE		430
297 #define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE		431
298 #define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE		432
299 #define CMDQ_EVENT_DISP_AAL0_FRAME_DONE			433
300 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0		434
301 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1		435
302 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2		436
303 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3		437
304 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4		438
305 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5		439
306 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6		440
307 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7		441
308 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8		442
309 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9		443
310 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10	444
311 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11	445
312 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12	446
313 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13	447
314 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14	448
315 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15	449
316 #define CMDQ_EVENT_DSI0_TE_ENG_EVENT			450
317 #define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT			451
318 #define CMDQ_EVENT_DSI0_DONE_ENG_EVENT			452
319 #define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT	453
320 #define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT		454
321 #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT	455
322 #define CMDQ_EVENT_DISP_OVL2_2L_RST_DONE_ENG_EVENT	456
323 #define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT		457
324 #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT	458
325 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0		459
326 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1		460
327 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2		461
328 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3		462
329 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4		463
330 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5		464
331 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6		465
332 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7		466
333 #define CMDQ_MAX_HW_EVENT				512
334 
335 #endif
336