1*46d613fdS周琰杰 (Zhou Yanjie) /* SPDX-License-Identifier: GPL-2.0-only */ 2*46d613fdS周琰杰 (Zhou Yanjie) /* 3*46d613fdS周琰杰 (Zhou Yanjie) * This header provides macros for X2000 DMA bindings. 4*46d613fdS周琰杰 (Zhou Yanjie) * 5*46d613fdS周琰杰 (Zhou Yanjie) * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 6*46d613fdS周琰杰 (Zhou Yanjie) */ 7*46d613fdS周琰杰 (Zhou Yanjie) 8*46d613fdS周琰杰 (Zhou Yanjie) #ifndef __DT_BINDINGS_DMA_X2000_DMA_H__ 9*46d613fdS周琰杰 (Zhou Yanjie) #define __DT_BINDINGS_DMA_X2000_DMA_H__ 10*46d613fdS周琰杰 (Zhou Yanjie) 11*46d613fdS周琰杰 (Zhou Yanjie) /* 12*46d613fdS周琰杰 (Zhou Yanjie) * Request type numbers for the X2000 DMA controller (written to the DRTn 13*46d613fdS周琰杰 (Zhou Yanjie) * register for the channel). 14*46d613fdS周琰杰 (Zhou Yanjie) */ 15*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_AUTO 0x8 16*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART5_TX 0xa 17*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART5_RX 0xb 18*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART4_TX 0xc 19*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART4_RX 0xd 20*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART3_TX 0xe 21*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART3_RX 0xf 22*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART2_TX 0x10 23*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART2_RX 0x11 24*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART1_TX 0x12 25*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART1_RX 0x13 26*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART0_TX 0x14 27*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART0_RX 0x15 28*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_SSI0_TX 0x16 29*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_SSI0_RX 0x17 30*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_SSI1_TX 0x18 31*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_SSI1_RX 0x19 32*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C0_TX 0x24 33*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C0_RX 0x25 34*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C1_TX 0x26 35*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C1_RX 0x27 36*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C2_TX 0x28 37*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C2_RX 0x29 38*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C3_TX 0x2a 39*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C3_RX 0x2b 40*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C4_TX 0x2c 41*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C4_RX 0x2d 42*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C5_TX 0x2e 43*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_I2C5_RX 0x2f 44*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART6_TX 0x30 45*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART6_RX 0x31 46*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART7_TX 0x32 47*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART7_RX 0x33 48*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART8_TX 0x34 49*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART8_RX 0x35 50*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART9_TX 0x36 51*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_UART9_RX 0x37 52*46d613fdS周琰杰 (Zhou Yanjie) #define X2000_DMA_SADC_RX 0x38 53*46d613fdS周琰杰 (Zhou Yanjie) 54*46d613fdS周琰杰 (Zhou Yanjie) #endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */ 55