1*5b7b41cbS周琰杰 (Zhou Yanjie) /* SPDX-License-Identifier: GPL-2.0-only */ 2*5b7b41cbS周琰杰 (Zhou Yanjie) /* 3*5b7b41cbS周琰杰 (Zhou Yanjie) * This header provides macros for JZ4775 DMA bindings. 4*5b7b41cbS周琰杰 (Zhou Yanjie) * 5*5b7b41cbS周琰杰 (Zhou Yanjie) * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 6*5b7b41cbS周琰杰 (Zhou Yanjie) */ 7*5b7b41cbS周琰杰 (Zhou Yanjie) 8*5b7b41cbS周琰杰 (Zhou Yanjie) #ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__ 9*5b7b41cbS周琰杰 (Zhou Yanjie) #define __DT_BINDINGS_DMA_JZ4775_DMA_H__ 10*5b7b41cbS周琰杰 (Zhou Yanjie) 11*5b7b41cbS周琰杰 (Zhou Yanjie) /* 12*5b7b41cbS周琰杰 (Zhou Yanjie) * Request type numbers for the JZ4775 DMA controller (written to the DRTn 13*5b7b41cbS周琰杰 (Zhou Yanjie) * register for the channel). 14*5b7b41cbS周琰杰 (Zhou Yanjie) */ 15*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_I2S0_TX 0x6 16*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_I2S0_RX 0x7 17*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_AUTO 0x8 18*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SADC_RX 0x9 19*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART3_TX 0x0e 20*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART3_RX 0x0f 21*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART2_TX 0x10 22*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART2_RX 0x11 23*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART1_TX 0x12 24*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART1_RX 0x13 25*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART0_TX 0x14 26*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_UART0_RX 0x15 27*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SSI0_TX 0x16 28*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SSI0_RX 0x17 29*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_MSC0_TX 0x1a 30*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_MSC0_RX 0x1b 31*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_MSC1_TX 0x1c 32*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_MSC1_RX 0x1d 33*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_MSC2_TX 0x1e 34*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_MSC2_RX 0x1f 35*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_PCM0_TX 0x20 36*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_PCM0_RX 0x21 37*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SMB0_TX 0x24 38*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SMB0_RX 0x25 39*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SMB1_TX 0x26 40*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SMB1_RX 0x27 41*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SMB2_TX 0x28 42*5b7b41cbS周琰杰 (Zhou Yanjie) #define JZ4775_DMA_SMB2_RX 0x29 43*5b7b41cbS周琰杰 (Zhou Yanjie) 44*5b7b41cbS周琰杰 (Zhou Yanjie) #endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */ 45