xref: /linux/include/dt-bindings/clock/ultrarisc,dp1000-clk.h (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1*e1d57ac7SJia Wang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*e1d57ac7SJia Wang #ifndef _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H
3*e1d57ac7SJia Wang #define _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H
4*e1d57ac7SJia Wang 
5*e1d57ac7SJia Wang #define DP1000_CLK_SYSPLL		0
6*e1d57ac7SJia Wang #define DP1000_CLK_SYSPLL_DIV2		1
7*e1d57ac7SJia Wang #define DP1000_CLK_SUBSYS		2
8*e1d57ac7SJia Wang #define DP1000_CLK_GMAC			3
9*e1d57ac7SJia Wang #define DP1000_CLK_UART_ROOT		4
10*e1d57ac7SJia Wang #define DP1000_CLK_I2C_ROOT		5
11*e1d57ac7SJia Wang #define DP1000_CLK_SPI_ROOT		6
12*e1d57ac7SJia Wang #define DP1000_CLK_PCIE_DBI		7
13*e1d57ac7SJia Wang #define DP1000_CLK_PCIEX4_CORE		8
14*e1d57ac7SJia Wang #define DP1000_CLK_PCIEX16_CORE		9
15*e1d57ac7SJia Wang #define DP1000_CLK_PCIE_AUX		10
16*e1d57ac7SJia Wang #define DP1000_CLK_UART0		11
17*e1d57ac7SJia Wang #define DP1000_CLK_UART1		12
18*e1d57ac7SJia Wang #define DP1000_CLK_UART2		13
19*e1d57ac7SJia Wang #define DP1000_CLK_UART3		14
20*e1d57ac7SJia Wang #define DP1000_CLK_I2C0			15
21*e1d57ac7SJia Wang #define DP1000_CLK_I2C1			16
22*e1d57ac7SJia Wang #define DP1000_CLK_I2C2			17
23*e1d57ac7SJia Wang #define DP1000_CLK_I2C3			18
24*e1d57ac7SJia Wang #define DP1000_CLK_SPI0			19
25*e1d57ac7SJia Wang #define DP1000_CLK_SPI1			20
26*e1d57ac7SJia Wang 
27*e1d57ac7SJia Wang #endif /* _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H */
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