1*ffa81a03SNobuhiro Iwamatsu /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ffa81a03SNobuhiro Iwamatsu 3*ffa81a03SNobuhiro Iwamatsu #ifndef _DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ 4*ffa81a03SNobuhiro Iwamatsu #define _DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ 5*ffa81a03SNobuhiro Iwamatsu 6*ffa81a03SNobuhiro Iwamatsu /* PLL */ 7*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIPLL0 0 8*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIPLL1 1 9*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIDNNPLL 2 10*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIETHERPLL 3 11*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIDDRCPLL 4 12*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIVOIFPLL 5 13*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_PLL_PIIMGERPLL 6 14*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_NR_PLL 7 15*ffa81a03SNobuhiro Iwamatsu 16*ffa81a03SNobuhiro Iwamatsu /* Clocks */ 17*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPLL1_DIV1 0 18*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPLL1_DIV2 1 19*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPLL1_DIV4 2 20*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIDNNPLL_DIV1 3 21*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC_PHY_PLL0 4 22*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC_PHY_PLL1 5 23*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_D_PHYPLL 6 24*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PHY_PCIEPLL 7 25*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_CA53CL0 8 26*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_CA53CL1 9 27*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISDMAC 10 28*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPDMAC0 11 29*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPDMAC1 12 30*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIWRAM 13 31*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC0 14 32*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC0_SCLK 15 33*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC0_NCLK 16 34*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC0_MCLK 17 35*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC0_APBCLK 18 36*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC1 19 37*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC1_SCLK 20 38*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC1_NCLK 21 39*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC1_MCLK 22 40*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDRC1_APBCLK 23 41*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_HOX 24 42*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PCIE_MSTR 25 43*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PCIE_AUX 26 44*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIINTC 27 45*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIETHER_BUS 28 46*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI0 29 47*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI1 30 48*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI2 31 49*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI3 32 50*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI4 33 51*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI5 34 52*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISPI6 35 53*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIUART0 36 54*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIUART1 37 55*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIUART2 38 56*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIUART3 39 57*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C0 40 58*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C1 41 59*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C2 42 60*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C3 43 61*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C4 44 62*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C5 45 63*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C6 46 64*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C7 47 65*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PII2C8 48 66*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIGPIO 49 67*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPGM 50 68*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPCMIF 51 69*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPCMIF_AUDIO_O 52 70*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPCMIF_AUDIO_I 53 71*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PICMPT0 54 72*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PICMPT1 55 73*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PITSC 56 74*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIUWDT 57 75*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISWDT 58 76*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_WDTCLK 59 77*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISUBUS_150M 60 78*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PISUBUS_300M 61 79*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIPMU 62 80*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIGPMU 63 81*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PITMU 64 82*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_WRCK 65 83*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIEMM 66 84*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIMISC 67 85*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIGCOMM 68 86*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIDCOMM 69 87*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PICKMON 70 88*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIMBUS 71 89*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_SBUSCLK 72 90*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDR0_APBCLKCLK 73 91*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DDR1_APBCLKCLK 74 92*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DSP0_PBCLK 75 93*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DSP1_PBCLK 76 94*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DSP2_PBCLK 77 95*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DSP3_PBCLK 78 96*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DSVIIF0_APBCLK 79 97*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF0_APBCLK 80 98*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF0_CFGCLK 81 99*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF1_APBCLK 82 100*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF1_CFGCLK 83 101*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF2_APBCLK 84 102*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF2_CFGCLK 85 103*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF3_APBCLK 86 104*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF3_CFGCLK 87 105*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF4_APBCLK 88 106*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF4_CFGCLK 89 107*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF5_APBCLK 90 108*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIF5_CFGCLK 91 109*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF_SBUSCLK 92 110*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF_PROCCLK 93 111*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF_DPHYCFGCLK 94 112*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DNN0 95 113*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_STMAT 96 114*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_HWA0 97 115*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_AFFINE0 98 116*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_HAMAT 99 117*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_SMLDB 100 118*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_HWA0_ASYNC 101 119*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_HWA2 102 120*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_FLMAT 103 121*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PYRAMID 104 122*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_HWA2_ASYNC 105 123*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_DSP0 106 124*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFBS0 107 125*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFBS0_L2ISP 108 126*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFBS0_L1ISP 109 127*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFBS0_PROC 110 128*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFBS1 111 129*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFBS2 112 130*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFOP_MBUS 113 131*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VIIFOP0_PROC 114 132*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIETHER_2P5M 115 133*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIETHER_25M 116 134*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIETHER_50M 117 135*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIETHER_125M 118 136*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF0_DPHYCFG 119 137*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF0_PROC 120 138*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF0_SBUS 121 139*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF0_DSIREF 122 140*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_VOIF0_PIXEL 123 141*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_PIREFCLK 124 142*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_SBUS 125 143*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_CLK_BUSLCK 126 144*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_NR_CLK 127 145*ffa81a03SNobuhiro Iwamatsu 146*ffa81a03SNobuhiro Iwamatsu /* Reset */ 147*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIETHER_2P5M 0 148*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIETHER_25M 1 149*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIETHER_50M 2 150*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIETHER_125M 3 151*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_HOX 4 152*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PCIE_MSTR 5 153*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PCIE_AUX 6 154*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIINTC 7 155*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIETHER_BUS 8 156*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI0 9 157*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI1 10 158*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI2 11 159*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI3 12 160*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI4 13 161*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI5 14 162*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PISPI6 15 163*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIUART0 16 164*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIUART1 17 165*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIUART2 18 166*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIUART3 19 167*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C0 20 168*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C1 21 169*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C2 22 170*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C3 23 171*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C4 24 172*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C5 25 173*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C6 26 174*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C7 27 175*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PII2C8 28 176*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PIPCMIF 29 177*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_PICKMON 30 178*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_RESET_SBUSCLK 31 179*ffa81a03SNobuhiro Iwamatsu #define TMPV770X_NR_RESET 32 180*ffa81a03SNobuhiro Iwamatsu 181*ffa81a03SNobuhiro Iwamatsu #endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */ 182