189727949SDinh Nguyen /* SPDX-License-Identifier: GPL-2.0 */ 289727949SDinh Nguyen /* 389727949SDinh Nguyen * Copyright (C) 2017, Intel Corporation 489727949SDinh Nguyen */ 589727949SDinh Nguyen 689727949SDinh Nguyen #ifndef __STRATIX10_CLOCK_H 789727949SDinh Nguyen #define __STRATIX10_CLOCK_H 889727949SDinh Nguyen 989727949SDinh Nguyen /* fixed rate clocks */ 1089727949SDinh Nguyen #define STRATIX10_OSC1 0 1189727949SDinh Nguyen #define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1 1289727949SDinh Nguyen #define STRATIX10_CB_INTOSC_LS_CLK 2 1389727949SDinh Nguyen #define STRATIX10_F2S_FREE_CLK 3 1489727949SDinh Nguyen 1589727949SDinh Nguyen /* fixed factor clocks */ 1689727949SDinh Nguyen #define STRATIX10_L4_SYS_FREE_CLK 4 1789727949SDinh Nguyen #define STRATIX10_MPU_PERIPH_CLK 5 1889727949SDinh Nguyen #define STRATIX10_MPU_L2RAM_CLK 6 1989727949SDinh Nguyen #define STRATIX10_SDMMC_CIU_CLK 7 2089727949SDinh Nguyen 2189727949SDinh Nguyen /* PLL clocks */ 2289727949SDinh Nguyen #define STRATIX10_MAIN_PLL_CLK 8 2389727949SDinh Nguyen #define STRATIX10_PERIPH_PLL_CLK 9 2489727949SDinh Nguyen #define STRATIX10_BOOT_CLK 10 2589727949SDinh Nguyen 2689727949SDinh Nguyen /* Periph clocks */ 2789727949SDinh Nguyen #define STRATIX10_MAIN_MPU_BASE_CLK 11 2889727949SDinh Nguyen #define STRATIX10_MAIN_NOC_BASE_CLK 12 2989727949SDinh Nguyen #define STRATIX10_MAIN_EMACA_CLK 13 3089727949SDinh Nguyen #define STRATIX10_MAIN_EMACB_CLK 14 3189727949SDinh Nguyen #define STRATIX10_MAIN_EMAC_PTP_CLK 15 3289727949SDinh Nguyen #define STRATIX10_MAIN_GPIO_DB_CLK 16 3389727949SDinh Nguyen #define STRATIX10_MAIN_SDMMC_CLK 17 3489727949SDinh Nguyen #define STRATIX10_MAIN_S2F_USR0_CLK 18 3589727949SDinh Nguyen #define STRATIX10_MAIN_S2F_USR1_CLK 19 3689727949SDinh Nguyen #define STRATIX10_MAIN_PSI_REF_CLK 20 3789727949SDinh Nguyen 3889727949SDinh Nguyen #define STRATIX10_PERI_MPU_BASE_CLK 21 3989727949SDinh Nguyen #define STRATIX10_PERI_NOC_BASE_CLK 22 4089727949SDinh Nguyen #define STRATIX10_PERI_EMACA_CLK 23 4189727949SDinh Nguyen #define STRATIX10_PERI_EMACB_CLK 24 4289727949SDinh Nguyen #define STRATIX10_PERI_EMAC_PTP_CLK 25 4389727949SDinh Nguyen #define STRATIX10_PERI_GPIO_DB_CLK 26 4489727949SDinh Nguyen #define STRATIX10_PERI_SDMMC_CLK 27 4589727949SDinh Nguyen #define STRATIX10_PERI_S2F_USR0_CLK 28 4689727949SDinh Nguyen #define STRATIX10_PERI_S2F_USR1_CLK 29 4789727949SDinh Nguyen #define STRATIX10_PERI_PSI_REF_CLK 30 4889727949SDinh Nguyen 4989727949SDinh Nguyen #define STRATIX10_MPU_FREE_CLK 31 5089727949SDinh Nguyen #define STRATIX10_NOC_FREE_CLK 32 5189727949SDinh Nguyen #define STRATIX10_S2F_USR0_CLK 33 5289727949SDinh Nguyen #define STRATIX10_NOC_CLK 34 5389727949SDinh Nguyen #define STRATIX10_EMAC_A_FREE_CLK 35 5489727949SDinh Nguyen #define STRATIX10_EMAC_B_FREE_CLK 36 5589727949SDinh Nguyen #define STRATIX10_EMAC_PTP_FREE_CLK 37 5689727949SDinh Nguyen #define STRATIX10_GPIO_DB_FREE_CLK 38 5789727949SDinh Nguyen #define STRATIX10_SDMMC_FREE_CLK 39 5889727949SDinh Nguyen #define STRATIX10_S2F_USER1_FREE_CLK 40 5989727949SDinh Nguyen #define STRATIX10_PSI_REF_FREE_CLK 41 6089727949SDinh Nguyen 6189727949SDinh Nguyen /* Gate clocks */ 6289727949SDinh Nguyen #define STRATIX10_MPU_CLK 42 6389727949SDinh Nguyen #define STRATIX10_L4_MAIN_CLK 43 6489727949SDinh Nguyen #define STRATIX10_L4_MP_CLK 44 6589727949SDinh Nguyen #define STRATIX10_L4_SP_CLK 45 6689727949SDinh Nguyen #define STRATIX10_CS_AT_CLK 46 6789727949SDinh Nguyen #define STRATIX10_CS_TRACE_CLK 47 6889727949SDinh Nguyen #define STRATIX10_CS_PDBG_CLK 48 6989727949SDinh Nguyen #define STRATIX10_CS_TIMER_CLK 49 7089727949SDinh Nguyen #define STRATIX10_S2F_USER0_CLK 50 7189727949SDinh Nguyen #define STRATIX10_S2F_USER1_CLK 51 7289727949SDinh Nguyen #define STRATIX10_EMAC0_CLK 52 7389727949SDinh Nguyen #define STRATIX10_EMAC1_CLK 53 7489727949SDinh Nguyen #define STRATIX10_EMAC2_CLK 54 7589727949SDinh Nguyen #define STRATIX10_EMAC_PTP_CLK 55 7689727949SDinh Nguyen #define STRATIX10_GPIO_DB_CLK 56 7789727949SDinh Nguyen #define STRATIX10_SDMMC_CLK 57 7889727949SDinh Nguyen #define STRATIX10_PSI_REF_CLK 58 7989727949SDinh Nguyen #define STRATIX10_USB_CLK 59 8089727949SDinh Nguyen #define STRATIX10_SPI_M_CLK 60 8189727949SDinh Nguyen #define STRATIX10_NAND_CLK 61 82*3b5015c4SDinh Nguyen #define STRATIX10_NAND_X_CLK 62 83*3b5015c4SDinh Nguyen #define STRATIX10_NAND_ECC_CLK 63 84*3b5015c4SDinh Nguyen #define STRATIX10_NUM_CLKS 64 8589727949SDinh Nguyen 8689727949SDinh Nguyen #endif /* __STRATIX10_CLOCK_H */ 87